EEVblog Electronics Community Forum
Electronics => PCB/EDA/CAD => Altium Designer => Topic started by: ricko_uk on May 06, 2020, 03:27:42 am
-
Hi,
in 20 years of using Altium this has never happened to me before...
I have a large complex FLAT design (i.e. no multi-channel nor hierarchical) which design which I used plenty of time as base design for other projects. It always compiled perfectly with no errors and so did all projects I derived from it.
Today I used it again to start a new project and I added various components. I kept compiling all along and it was all ok every time I compiled it. Then after adding a couple of more components it suddenly started giving more than 100 (!!) errors "Duplicate net name wires xxxx". That occurs for 90% of the nets that never gave any errors before and that I have not touched (nor connected to) when adding those few new components.
That occurs whether I select the project to be flat configuration or automatic. In either case, being a flat design, any duplicate net labels should just connect together not give an error.
I removed the components most recently added (since the previous succesfull compile) just in case they cause it, but those errors remained. Hundreds of them all addressing hundreds of nets which previously (for years!) always compiled without any errors.
Anyway... Any suggestions what it could be and how to solve it? Maybe some "clean net" or "hard recompile" type solution?
Any suggestion greatly appreciated!! :)
Many thanks
-
Is that the exact error message? Can you show a screenshot of the error window?
If it's such a large design, presumably it's multiple sheets? How are you establishing connectivity between sheets?
Can you open the original file again, and copy and paste the new elements into it?
-
Thank you AJB,
please see attached is a screenshot with the errors. It is a large design but flat, no need to make it hirarchical.
Those nets generating errors:
1) have not been touched AT ALL and never gave any error for literally years of reusing that base design
2) do not connect to any of the new nets or components which I added yesterday to expand the design
3) are in sheets which have not even been touched at all in the new mods. Some sheets have not even been opened.
4) 90% of them (take for example net EECLK highlighted) have only 2 connecting parts.
As mentioned previously, it was compiling without any errors all along as I was expanding the original design in the past couple of days. Then suddenly after adding two o three components from the library (maybe some general passives or a connector) it suddenly generated hundreds of those errors.
Any suggestion about:
a) what it might create them
b) how to solve it?
Many thanks
-
what is your top-level document? Check your project settings. You may have altered the mode to strict. other possibilities : net name suffixes based on document turned off
-
Also try Tools/Convert/Reset Component Unique IDs, in case anything got screwed up (this can happen with duplicated schematic files; though I don't think it should have any effect on named nets and connectivity?).
Also FYI, consider using off-sheet connectors or ports to connect between sheets, and use wires (preferred) or net labels (less preferred) to connect between components within a sheet. This improves readability. They work basically identically in a flat design. Using ports, you also have an easy "in" for reusing the sheets in a hierarchical design.
Tim
-
Hi ricko_uk... did you ever sort this out? same problem on altium 20.
-
Hi frogblender,
yes, for every sheet I selected all in that sheet then cut and pasted pack in the same sheet. Then saved.
Hope that helps. :)