Electronics > Altium Designer

Altium, JLCPCB and 0.65mm BGA


Has anyone managed to reconcile the design rules for Altium with JLC's BGA capabilities ? Or have any bright ideas about what can be tweaked to make things work ?

Even using their in-pad vias, I'm not managing to get traces out "neatly" in a traditional fan-out, and I'm not sure if it's my interpretation of their rules, or it's just not going to work. Here's an example of what I mean, the top lines fan out fine, but as soon as vias are introduced, I seem to need a rather excessive detour around them to get the signal past...

Design rules for clearance look like:

And the clearances from JLCPCB look like:

Any hints towards what I'm missing would be appreciated :)

So its not possible using dogbone?
I wouldn't worry about if it looks neat or not, either you have the space to break out all the pads or you don't.

I don't know if your rules are correct as PTH to track is 0.33mm and via to track is 0.254mm here: jlcpcb.com/capabilities/pcb-capabilities

https://www.eevblog.com/forum/fpga/custom-spartan-7-board-for-beginners/ (asmi example project with spartan 7 bga + dogbone)

No, it doesn't work with dogbone either. The "neatness" was more about it looking wrong than any real desire for it to look nice :)

I'll have a look at the links you posted, thanks :) If other people are managing 0.65mm BGA at JLC then I ought to be able to, too ...

I think the PTH<->Track and Via<->Track you're looking at are the "general case". They have a page here talking about their recommended BGA configs, and this is a 4 (maybe 6) layer board.

What hole size did you use, 0.2mm?
The quote page offers 0.15, 0.2, 0.25, and 0.3mm depending on how much you want to pay. 0.2mm looks like its already a premium option.

edit: here is the BGA page https://jlcpcb.com/help/article/243-BGA-Design-Guidelines---PCB-Layout-Recommendations-for-BGA-packages

They offer 0.15, but 0.2 is the standard one I think, and yeah, that's the page I was looking at also. Perhaps I'll try the 0.15mm drills and see how I go with them.


So looking at that page again, it's talking about the 0.2mm drill / 0.3mm via, but if you *do* use 0.15mm drills, then the via drops to 0.25mm, meaning that for every ball-pair I have:

0.25mm (each half of the BGA pad, 2 of them, one each side)
0.127mm (for the trace<-> via clearance on the left)
0.127mm (for the trace <-> via clearance on the right)
0.09mm (3.5 mil trace)

= 0.594mm, which is less than the 0.65mm separation (actually that will still fit using 0.2/0.3 mm via spacing, just). So I'm doing something wrong with Altium's rules I guess...

[edit, take 2]

So I figured it out. It wasn't the via or trace rules, it was the 'hole' clearance rules. It was set to 0.25mm, which is rather large, and in fact the distance in the BGA recommendations is 0.2mm. Putting 0.2mm in across the board for 'hole' still wouldn't quite fit a trace through two of the 0.2mm/0.3mm vias, but using 0.15mm/0.25mm vias now works, so I guess I pay up :) 


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