How to prevent silkscreen from overlapping during panelization?

[mrflibble]

I'm trying to do some panelization using an Embedded Board Array, and that is working nicely except for one thing.

There's an angled 5x2 header on the original PCB, and as such the silkscreen for the pins go outside of the board outline. Now for the single PCB that's no real issue. Just define the board outline, toss gerbers over the wall and problem solved. But as you can see in the attached screenshot the silkscreen from the angled connector is showing up on the neighbouring pcb in the array.

Is there any systematic solution for this? I tried messing with polygons on keep-out layer but no luck. As a last resort I could change the header to a straight header, but that's a bit annoying and would mess up the BOM as well. Another way that would not involve messing up the BOM would be unlock the silkscreen primitives and delete the overlapping lines. So there are some workarounds, but what is the correct and clean way to solve this?

Any ideas?

[marshallh]

Click on the footprint > PCB Inspector window > Uncheck 'Lock Primitives' > Delete/shorten silkscreen to your heart's desire

[mrflibble]

Thanks, but ... as per the OP:

... Another way that would not involve messing up the BOM would be unlock the silkscreen primitives and delete the overlapping lines. So there are some workarounds, but what is the correct and clean way to solve this?

And in the meantime I did just that, see attached. But preferably I'd have some way to only have it copy stuff that falls inside of the board shape of the original pcb, or some clever keep-out thingy.

[David_AVD]

I usually explode the offending component (tvc) and delete the bits I don't want.  I do save that version of the file separately with _tvc appended to the file name so I know it's not the original one.

I'd love to see a tool  that just limits the silkscreen to the defined edges.

[c4757p]

I think I'd just take the pin drawing out of the silkscreen permanently. What's the point of it? Perhaps move it to a different layer that doesn't actually print on the board, if you just want it for dimension when placing the part, but there's really no reason to illustrate the pins.

[mrflibble]

For this particular case I would tend to agree. But I meant the question in a more general sense.

Essentially: "How do I put a bounding box on what shall and what shall not be imported onto the embedded board array?"

[Jon Chandler]

Using Eagle, I draw the part of the silk screen extending off the board on the TDOC layer.  Then it's visible for positioning or documentation, but not included in the Gerber silkscreen layer.

[David_AVD]

It's not always straightforward though.  The same footprint can be positioned a different distance from the board edge depending on the application, so drawing part of it on another layer doesn't help in that case.

[mrflibble]

Right, sorted. I just hate playing a component-unlock-exploding-selecting-pointy-clickey monkey doing busy work. I prefer to let that happen to other people.

PCB Filter: InComponent('*') AND IsTrack AND (OnLayer('Top Overlay') OR OnLayer('Bottom Overlay')) AND ((X1 < 0.0) OR (X2 < 0.0) OR (Y1 < 0.0) OR (Y2 < 0.0)   OR   (X1 > 50.0) OR (X2 > 50.0) OR (Y1 > 50.0) OR (Y2 > 50.0))

PCB Inspector: [ x ] Keepout ... Width: 0mm

Result: see attached. No need to unlock components and select & edit, and it works for multiple offending components in one single action. The reason for setting width to 0 and enabling Keepout? Setting line width to 0 serves as a visual cue that makes it easy to spot this line is handled differently. And the keepout makes sure it doesn't show up on the gerbers. You can also do either 0 width OR Keepout and get workable gerbers. But this combo both keeps the lines out of the gerber while still making it easy to keep track of the design intent.

Still room for improvement ... main refinement would be a better query for selection. It's a bit verbose because I currently don't know a cleaner query syntax to check for ranges. And possibly an InLayerClass or something. It'll get tweaked as I go along and learn more about this Altium thingy, but this'll do for now.

[mrflibble]

And for future victims ... easier syntax to select those offending silkscreen tracks:

Create a room that overlaps the board shape. You only need a rectangle anyways since this is for an embedded board array.

PCB Filter: InAnyComponent && IsTrack && OnSilkscreen && NOT WithinRoom('WTFROOM')

That selects all those silkscreen tracks that fall outside of the board area, either entirely or partially. And then same as above. PCB Inspector: Enable Keepout, 0 width. Done. I wanted to learn how to use rooms & regions anyways, so this was the perfect excuse.

[David_AVD]

It's a shame that method removes the whole line(s) that extend outside the area instead of truncating them.  With the (more involved) exploding method I end up with the truncating effect.  Much more work of course and you end up with a separate file.

[mrflibble]

That is indeed the limitation of this method. Your edit method will result in a silkscreen that looks nicer. But personally I don't want to spend the time on something like that. If it can be scripted maybe, but I'm not going to edit it by hand. I've experimented a bit with rooms/regions/keepouts to get some sort of masking effect, but no luck.

[davide6893]

I too have the same problem. Do you know if any new features have been introduced in AD20 to do this? I would not want to make heavy changes on the single pcb, because I would also like to use it for other purposes and I am sorry to work on a duplicate, because if I have to make changes then they will not be synchronized on the copy, but I would like to work at the panel level. Thanks