Altium differential pair length match problems

[FPSUsername]

Hello,

I have issues using Altium's length tuning tools, they seem really incapable and not working well, both in Altium 17 and 19.

Lets start with the Interactive Diff Pair Length Tuning tool. From my understanding, you have to look at signal length and not routed length as routed length can give false information due to overlapping traces. As you can see in attachment 1, I want to match the length to (at that time when I didn't complete length matching yet) the longest pair (CH3).


When I select the target length in attachment 2, you can see that it selects the Averaged Length from pair CH3. (Keep in mind, I already matched the lengths of each trace in CH3).


When I start routing it, it is giving me the Routed Length instead of the Signal Length. This makes the Net Length Gauge useless. I have to look in the PCB tab for the signal length that it gets.

Going to the Interactive Pair Length Tuning you can see in attachment 3 that the Net Length Gauge actually shows the signal length that it's tuning.


Also in attachment 4 you can see that the target length is the signal length.


Furthermore, Altium has the option to reshape the Accordion, but only for the Interactive Pair Length Tuning tool. Why not for the Interactive Diff Pair Length Tuning tool as well?

Length matching takes more time than needed because I have to go back and forth every time to really match signal and pair lengths as the tuning happens at multiple places throughout the signal/pair's path.

[Bud]

Attachments?

[FPSUsername]

That's weird, they seem to be deleted. I'll upload fresh ones

[ajb]

Maybe try xSignals?  Takes a bit more setup since they need to be defined first, but IME the calculations are a lot more useful (segments with flyby connections, for instance).  I've never used them with diffpairs, though.

[Pseudobyte]

The problem is you have no rules defined to enforce matched length.

Setup a rule for Matched Lengths and you should have no problems

https://www.altium.com/documentation/17.1/display/ADES/((Length+Tuning))_AD

[Pseudobyte]

A bit of help for how this can be done:

Schematic:

Setup a DiffPairClass for the diff pairs you want to tune against one another.





PCB:

Setup Rules





Results:

[FPSUsername]

Thank you for the help.

@ajb from my understanding, xSignals are used to connect more than two nodes, in my case I don't have more than two nodes (I do in my CSI-2 diff. class).

@Pseudobyte At first, I followed what you did in your post and this is how my results look like:


It is still trying to match routed length while the rule uses signal length.
I cleaned up the whole trace of any duplicates (traces under other traces) and the routed length is still far from equal to the signal length.
I am not sure what I'm doing wrong here.

Secondly, I wonder why altium's miltered lines allow 90 degree bends when using large amplitude and space settings. From what I know, you want to avoid any sharp cornering with high speed signals due to reflection. I've only seen 90 degree bends in PCB antennas, which I'm not sure how they work.

Lastly, a weird issue in 17 is that a blanket doesn't do much. In the documentation of Altium 18/19 the blanket usage is very clean. A blanket can cover all signals with just one directive. This way you don't have to add a directive to every single line. Unfortunately in 17 you still have to do that, otherwise the compiler will spit out errors.

[Pseudobyte]

Oh did not realize that was what you were trying to accomplish. Apologies...yes the best way to accomplish this would be xSignals.

[FPSUsername]

Oh did not realize that was what you were trying to accomplish. Apologies...yes the best way to accomplish this would be xSignals.

As I stated in my previous post, aren't xSignals used to connect (for example) one output pin to two input pins? As seen in The Challenge from the documents, it's used to create a balanced T topology.
I on the other hand only have one output and one input.
I do use xSignals on my CSI-2 class since the termination resistors are placed on the PCB and aren't internally build in to the FPGA (those are reserved for the subLVDS class). xSignals do seem to report the same signal and routed length, so any length matching doesn't create weird problems.

[Pseudobyte]

From that same link:

"An xSignal is essentially a designer-defined signal path between 2 nodes - these can be 2 nodes within the same net, or they can be 2 nodes in associated nets separated by a component. The xSignal can then be used to scope relevant design rules such as Length and Matched Length, which will then be obeyed during design tasks, such as interactive length tuning."

Then also read the section titled Accurate Length Calculations.