Altium Test Points

[sacherjj]

I've not used Altium's Testpoint Manager until the design I just sent off for fabrication.   I can't figure out why all of my test points are illegal.

Rule for AssemblyTestpoint:
Used Rule Scope Helper to have everything: "(IsPad And (OnTopLayer Or OnBottomLayer)) Or (IsVia) Or (IsPad And OnMultiLayer)"
Allowed Side on Top and Bottom
Min 1.016mm, Preferred 1.524mm, Max 2.54mm

I'm using vias with 1.524mm diameter, 0.508mm hole and soldermask expansion of -0.5mm on bottom and 0mm on top.  This gives a clean hole only exposed on top surface and a full copper on bottom.

Is there a place where Altium tells you WHY the test points are illegal?  I have read through the test point docs out there and see only about creating them, but nothing about fixing illegal ones.
Setting Testpoint Settings to Fabrication and Assembly bottom.   

[T3sl4co1l]

Don't suppose you could share your project (privately?)?..

These are the rules I use; I typically use either a complete testpoint component (so the testpoints are there, physically, during placement and routing), or a reasonably sized via or SMT pad, with reasonable spacing.  (The "NoTest" class is there for nets that shouldn't (or can't) be tested, e.g., superfluous single-pin nets, cramped logic pins surrounded by resistor networks, etc.  The other "usage" rule you see just allows multiple testpoints in net class "Power".)

The pads/vias themselves are generally assigned manually, since the manager might pick inappropriate or unintended points.  (I don't bother with manually assigning fab, I let it do that exclusively.)  If all your vias/pads are a unique size, this is very quick with a query.

In this case, test is one side (which is preferred), and pads/vias are only assigned that side.  You'll get an error if they're assigned to the other.

I leave all testpoints un-tented, both sides.  I doubt Altium checks for soldermask encroaching, at least on the far side... but maybe that's what you're doing that's different and throwing the problem?

Your pad/via size sounds okay, though I might suggest a smaller hole, and optionally a smaller pad, just so you aren't wasting so much space..

Honestly, I don't know how difficult it is to test with large vs. small pads, or what that translates to in test fixture NRE / production costs, so it could be my rules are too tight for a more economically-minded design...

Tim

[sacherjj]

I like the NoTest net idea, I'll integrate that.  I'll look through this again to see what I missed.

The hole size for my current design is to be the same as my normal vias, as I don't expect to use test points for anything but manual probing.  But I'm using this as learning for setting up as real fixture points in a future design.

[daffy205]

Hello Tim,

Could you tell me how you define your rule AssemblyTestPointIUsage_Power to allows multiple testpoint on the same netname!

[T3sl4co1l]

That goes something like,

Query:
InNetClass('Power') AND (all the query from the regular rule)

Settings:
Same, except "allow multiple testpoints" ticked

Tim

[daffy205]

 
Thanks for the fast reply, but i don`t understand well the meaning of (all the query from the regular rule) could you give me some example of that! for me right now my query for AssemblyTestPointIUsage is set to All, same thing for the Assembly Tespoint style rules!

Regards!

[T3sl4co1l]

I mean the query that's pictured.  If you have "All", then nothing more is necessary.

Tim

[daffy205]

That`s what i`m thinking! Thanks a lot for your help!

Regards!

jf