Author Topic: Altrium vias and poligon clerance  (Read 1512 times)

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Offline milionarioTopic starter

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Altrium vias and poligon clerance
« on: October 25, 2017, 01:53:27 pm »
Hi, I've a problem with vias, through hole pads and poligon in altium; in particular in some instances (as you can see in the first figure) there is almost no clearance between the anular ring and th poligon's copper, in the second screenshot you can see my clearance layout rules

Is there someone that can shed some light on this issue?

thanks
 

Offline T3sl4co1l

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    • Seven Transistor Labs
Re: Altrium vias and poligon clerance
« Reply #1 on: October 25, 2017, 03:42:18 pm »
Remember to always repour polygons.

Polygon-to-via connections are governed by the PolygonConnect design rule.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline milionarioTopic starter

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Re: Altrium vias and poligon clerance
« Reply #2 on: October 25, 2017, 06:43:43 pm »
i'have repour without succes, but I'have solved the problem

I created a new rule between poligon and vias with a differente clerance
 


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