Author Topic: Unrouted nets DRC error when routed (fixed)  (Read 1207 times)

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Offline sean0118Topic starter

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Unrouted nets DRC error when routed (fixed)
« on: April 28, 2020, 04:14:25 am »
This is fixed, just posting here to save other people time.

I started getting really weird DRC errors saying I had unrouted nets which were previously passing DRC. I could also see that they were routed correctly and pressing ctrl+H would select the whole net correctly.

After spending half a day I found there were regions with 0 width under the offending traces (see attachment).

Deleting these solved the issue, I'm not sure what created them, I think it might have been the teardrop generator as half of them were at T junctions.


This is in Altium 17 btw.
 

Online T3sl4co1l

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Re: Unrouted nets DRC error when routed (fixed)
« Reply #1 on: April 28, 2020, 06:26:43 am »
I did that recently too, must've hit P,R and clicked a few times before canceling out and doing P,T.  Oddness I was having was, nothing would select in the area, yet there was a snap point that the cursor would go to, and which other nets would refuse to route through.  Solved by looking for suspicious Region's on PCB List.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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Offline sean0118Topic starter

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Re: Unrouted nets DRC error when routed (fixed)
« Reply #2 on: April 28, 2020, 08:54:37 am »
I did that recently too, must've hit P,R and clicked a few times before canceling out and doing P,T.

That sounds like a similar issue, but mine was in a multichannel design though and the regions showed up under the same tracks in every room. I think it must have been something automated in my case, like the teardrop or clean all nets commands...

The other weird thing is the regions had the same nets as the tracks, but it still broke them somehow.


Altium...   ::)
 

Online T3sl4co1l

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Re: Unrouted nets DRC error when routed (fixed)
« Reply #3 on: April 28, 2020, 10:47:51 pm »
I've never seen teardropping fail like that, but admittedly that's only out of some thousands of autogenerated regions, and I try to be clean with my trace and pad geometry.  Could be some strange edge cases, who knows.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


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