Hi,
I just noticed today I was doing my DRCs with "Signal Integrity/Impedance" unchecked.
After checking the option, I can only assume the impedance constraint rules I applied to a few nets, simply doesn't seem to be applied.
I was expecting Altium would just modulate the impedance width to modulate the impedance.

I'm not necessarily trying to have perfect impedance matching (I think for that to happen the fab must control your stackup, and for *now* I want to use a generic stackup).
That said, I would expect there is some kind of functionnality to make Altium "decide" of the width of a trace so that it can match the impedance constraint, so that the DRC can pass (I understand there will be incertitudes, but not a >2x factor like I'm getting). I thought setting a rule would be sufficient, but it doesn't seem to have any impact.
TL;DR Is there a way to make Altium strictly apply the impedance rule I previously set (by imposing a width)?
Thanks!