EEVblog Electronics Community Forum
Electronics => PCB/EDA/CAD => Altium Designer => Topic started by: fjnieto15 on May 26, 2018, 02:17:10 pm
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Hi!
I need to fanout a big FPGA with a 1760 ball pads. I was wondering if there is a better way of doing this rather than adding 200000 layers.
Many of the signals are LVDS and they need to be shielded with ground planes above and below, which at the end it means that every signal layer I need for the fanout, I have to add two layers, one for signals and a ground plane. My layer count is up to 16 layers right now and I can't get to the inside of the FPGA yet.
Am I missing anything? I'd like to keep the cost relatively low.
Also, Xilinx provide some design rules in which there are some alternatives to escape two traces between two pads, is it possible to do this in Altium automatically?
Thanks for your help.
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Probably with blind and buried vias you can reduce the layer count.
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Low cost? Use two 900-pin BGAs. :-DD
If you can find one with blank spaces in the footprint (e.g., four rings of pads, then some open space, then some more pads in the center), you'll have better luck. I don't think these are very common with FPGAs, probably because you're paying so much for this chip already that a 16+ layer board isn't a big deal. They seem somewhat common in computer parts, usually system chips. Though I guess they don't have much choice with CPUs, which have been full pin/pad grids for a long time. Dunno.
Have you considered optimizing the layers for breakout? You only need so many power layers, and signal layers can be paired when their timing is not extreme (i.e. super low jitter).
Tim
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As an FYI: a reference plane does not have to be GND. AC doesn't care. A related power plane is just as well.
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Very best of luck with that. Stay sane and keep smiling ;D
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Very recently there was this exact same question on the KiCad forum:
forum.kicad.info
The answers there had a few good hints, including a link to a PDF with a lot of examples.
You can also have a look at the Olimexino A64.
It is a complete project with BGA's done in KiCad, and is on Github, including schematic / PCB layout.
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Probably with blind and buried vias you can reduce the layer count.
I've thought about it, but the prices of blind/buried vias are much higher than adding 2 more layers. I can't see the real advantage :-//
Low cost? Use two 900-pin BGAs. :-DD
If you can find one with blank spaces in the footprint (e.g., four rings of pads, then some open space, then some more pads in the center), you'll have better luck. I don't think these are very common with FPGAs, probably because you're paying so much for this chip already that a 16+ layer board isn't a big deal. They seem somewhat common in computer parts, usually system chips. Though I guess they don't have much choice with CPUs, which have been full pin/pad grids for a long time. Dunno.
Have you considered optimizing the layers for breakout? You only need so many power layers, and signal layers can be paired when their timing is not extreme (i.e. super low jitter).
Tim
I didn't mean low cost, but reducing the costs that can be reduced. It is a 40x25 cm board, nearly 3k$ so I would like to avoid it going over 5k$.
What do you mean by optimizing the layers for breakout?
As an FYI: a reference plane does not have to be GND. AC doesn't care. A related power plane is just as well.
So, do you mean that shielding the LVDS signals with power planes is as good as doing it with GND? Even with different voltages?
Very recently there was this exact same question on the KiCad forum:
forum.kicad.info
The answers there had a few good hints, including a link to a PDF with a lot of examples.
You can also have a look at the Olimexino A64.
It is a complete project with BGA's done in KiCad, and is on Github, including schematic / PCB layout.
I'll take a look, thanks!
Thanks for all of your answers and help
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So, do you mean that shielding the LVDS signals with power planes is as good as doing it with GND? Even with different voltages?
Yes. Just make sure that the power plane you choose is properly decoupled to ground with capacitors near both ends of your LVDS signals, and that the power plane doesn't have any cuts that the signals would cross (just like a ground plane). The return currents will happily go through the power plane, even if that power isn't actually used by the LVDS component.
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Did a bit of digging:
One of the fun things about KiCad is because of it's open-ness all kind of side projects pop up.
I have not used BGA's myself, but this semst o be a project to partly automate the fan-out of Big ball BGA's.
https://forum.kicad.info/t/bga-vias-as-part-of-footprint/10083/10 (https://forum.kicad.info/t/bga-vias-as-part-of-footprint/10083/10)
Bit it is of course limited to KiCad.
The thread I thought of was:
[url]https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3]https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3] [url]https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3 (http://[url=https://forum.kicad.info/t/0-4mm-bga-via-in-pad/5240/3)[/url]
and the document with examples is from lattice:
https://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/PT/PCBLayoutRecommendationsforBGAPackages.pdf?document_id=671 (https://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/PT/PCBLayoutRecommendationsforBGAPackages.pdf?document_id=671)
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I'd like to keep the cost relatively low.
It think that ship has sailed! :-).
I did a Xilinx device with 1738 balls. It took 20 layers are 10 reference planes to get it done. @13k USD for 10 boards (that were 6U card size) from Streamline. I used a fairly exotic dielectric (which allowed me to get 20 layers @ 0.0625" thickness).
If you haven't already, call the board house *now* to work out your stackup.
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Many of the signals are LVDS and they need to be shielded with ground planes above and below
What frequency?
How many pairs?
On which rows are the pins located?
Can the critical pairs be moved to outer row pins?
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I did a Xilinx device with 1738 balls. It took 20 layers are 10 reference planes to get it done.
Some time ago I heard / saw a story / interview ( Davey Jones / youtube?) about a guy who did PCB layout for a living. One of the projects he did was from a client who could not get a board layout in 12 layers, and came to him.
He said something like.
Well, I can do that for USD *** in a day or so, or I can redo the whole board for USD **** (4 digits) and then do it in 8 layers.
His client did some calculations, and he got the job to redo the board in 8 layers.
Anybody can draw a few traces on a PCB with a CAD package, but a good PCB layout is artwork.
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I did a Xilinx device with 1738 balls. It took 20 layers are 10 reference planes to get it done.
Well, I can do that for USD *** in a day or so, or I can redo the whole board for USD **** (4 digits) and then do it in 8 layers.
His client did some calculations, and he got the job to redo the board in 8 layers.
Anybody can draw a few traces on a PCB with a CAD package, but a good PCB layout is artwork.
awesome mind & skill that guy have, do you still have the link to that video?
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Hi Just did a XCVU13P with 2104 balls on 16 layers (8 singal layers 8 internal planes) .. with blind and micro via's (via pairs 1-2l, 1-3, 1-16, 14-16, 15-16)
is definitly doable..
with regards to the signaling, you need solid planes, but they do not need to GND.. the reference is not to ground, but to copper.. so you can reference the impedance from any potential.
good luckl
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Dave beat me to it. Have you fully excersized your pin swapping to bring the signals to the perimeter? LVDS is differential and while you still need a return path, it is only for a small percentage of the signal. You may want to run, or have someone run, SI simulations to see if the plane above and below are necessary. For adjacent LVDS layers, route orthogonally as you would for single ended signals.
Also, while a return path does not need to be GND, be sure to pepper the planes with high frequency caps. You want the impedance of that power plane to be as low (almost) as the GND plane at the frequencies of interest.