How to do curvy transitions between pads and tracks

[RedLion]

In a project I have recently taken over, I noticed the transitions between pads and tracks had, on most of them, rounded fillets (see the pictures).
Now, I am pretty much self taught in Altium and only use it occasionally it's not my main area of work.
My predecessor has left no documentation to speak of, so I can't follow his process and I can't contact him either.

Now I wondered if there is any reason to do this, other than the etching process. The board I am working on is a moderately high frequency FPGA (clock frequency 20MHz), which was a plug-in card with an Altera MAX10, but now will have a high power section as well. (I can't unfortunately get deeper into the project before talking to the boss-man because of patent reasons *groan*)
So, do these fillets serve a purpose, and if so, is there a good way to do this? They are "regions" in Altium, does that mean they were placed manually? Is that even necessary?

[olkipukki]

These called Teardrops, you can find how to make in menu Tools -> Teardrops

[RedLion]

Cool, thank you! Always difficult to find something if you don't know what it's called.
Not sure how useful this is going to be on a one off board, but as it's practically effortless to add, I'm going to do so anyways.

[T3sl4co1l]

SMT teardrops don't really mean anything, but on drilled holes, they buy a little more tolerance for positional error.  See IPC-2221.

Tim

[thm_w]

These look so inconsistent that they might be hand placed tracks. Note on the right hand side some vias have them some don't, and those are the more typical straight teardrop traces.

And yeah, I see zero reason to have them on those SMD pads. Especially at only 20MHz.

[T3sl4co1l]

Nah, those are autogenerated.  Teardrops are only drawn to the connecting trace, and that one via makes a dogleg with a very short trace, so little if any teardrop got drawn on it.  Teardrops can be drawn on intersections (see the +15V trace) but aren't drawn on corners (hence the jarring 45 degree inside angle right beside the tee).  Possibly DGND and LM_ON are missing teardrops because of proximity, or later editing.  Or they were generated that way; it's not the most accurate tool.

FYI, Altium keeps all its teardrops in one special union (or, one at a time at least).  If you modify the underlying geometry, it knows to delete objects in that union related to the affected objects.  Or it deletes the entire union and creates a new one when you generate them (but remember to clear existing ones, so you don't end up duplicating piles of objects).

You can see a list of objects on PCB List (select object type at the top), and a list of unions (and nets and other information) on PCB Panel.

BTW, you can see stacked objects in transparent view (see Layer Configuration).  I don't like opaque view, it hides far too much.

Tim

[RedLion]

These look so inconsistent that they might be hand placed tracks.

Knowing the guy who laid the PCB out, I highly doubt that. He's more the type of guy to click a button and let'er happen.

Note on the right hand side some vias have them some don't.

Maybe the PCB was modified after the fact and the second pass of teardroppin' got forgotten. Also suits the MO.

The person who designed this PCB did so as part of his PhD thesis, and also supervised my bachelor's thesis.
No, I in turn are working on my PhD, based on his previous research, but he since has left and his Uni e-mail is now defunct of course.

[pigrew]

I like how teardrops look, I usually will add them. I also feel like they should probably reduce electromigration and be mechanically stronger, but I have no evidence of either of those. 

One unrelated issue is that you have some vias-in-pad. During (reflow) assembly, it's possible that all of the solder will be wicked into the via, leaving your component's pad without any. Vias should be moved so that there is some solder mask between it and the pad.

[RedLion]

Yes, I noticed the layout was a bit sloppy. But I will make a completely new PCB based a modified schematic. I only looked at the old PCB for inspiration, as it will be my first 4-Layer board, also my first PCB with a complicated component such as an FPGA.

[intmpe]

This is a classic case of everything old is new again. This is the sort of thing you saw when boards were layed out using tape and film. Whether you use them will be insignificant generally. I personally would not use them for any SMT work just because I think they might screw paste and reflow. I recently had a component that was higher than it was wide - if the paste was not contained correctly it would topple over during reflow. The part maker gave specific guidance on pad layouts. You won't find them asking for teardrops in datasheets so its really a case of use at your own risk. But in the old days of tape and film it was probably preferable to avoid sharp corners simply for the etch process. But that is under control now.

[ajb]

This is a classic case of everything old is new again. This is the sort of thing you saw when boards were layed out using tape and film. Whether you use them will be insignificant generally. I personally would not use them for any SMT work just because I think they might screw paste and reflow. I recently had a component that was higher than it was wide - if the paste was not contained correctly it would topple over during reflow. The part maker gave specific guidance on pad layouts. You won't find them asking for teardrops in datasheets so its really a case of use at your own risk. But in the old days of tape and film it was probably preferable to avoid sharp corners simply for the etch process. But that is under control now.

Yes, I suspect that in many cases the thermal disadvantage of teardrops on very small chip components outweigh the advantages.  You're sort of trading soldering reliability for etching reliability, but unless you're pushing the limits of your board fab's capabilities the etching process probably doesn't care if you have teardrops or not.  A general rule of thumb is that small chip components (like 0402 and smaller, arguably even 0603s) shouldn't be directly connected to tracks wider than 10mil/0.25mm if possible, to limit the thermal mass of copper connected to the pad.  Obviously the likelihood of actual problems is highly dependent on the thermal layout of the board, but a teardrop obviously increases the amount of copper involved in the thermodynamics of the joint formation and could certainly have a negative impact on a design that is already close to the limits of manufacturablity. 

It's also generally recommended that tracks exit straight off the toe of the pad, or are symmetrical about the long axis of the part, also for solderability reasons.  A bunch of copper hanging off of one side of a chip component's pad increases the risk the component rotating during reflow.

Of course economical manufacturing is partially about only managing the risks that really matter, so there are lots of applications where none of these rules are consequential, and spending extra time to dot every single 'i' does not result in a measurably better (or more efficiently manufactured) product.  You can get away with a lot if you are only building a handful of something, but as quantity goes up the scrap/defect/rework rate translates to a larger and larger amount of money, and as a result you can attach more and more significant dollar amounts to all of the fussy little Design for Manufacture details.

[RedLion]

Well this is a one off prototype so...  ? Certainly not going to be too bothered about something that's at best adjacent to my research.

[ajb]

Well this is a one off prototype so...  ? Certainly not going to be too bothered about something that's at best adjacent to my research.

Yeah, don't sweat the teardrops then