Author Topic: [Solved] Cannot route on middle layers  (Read 1412 times)

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Offline blueskullTopic starter

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[Solved] Cannot route on middle layers
« on: October 14, 2019, 01:34:43 am »
I created a 4L design, which I started from top and bottom.
Today I was working on its middle layers, and Altium threw errors on clearance violation, which I didn't.

File is attached, if anyone can take a look at it.
The trace under investigation is 1V0 on the left bottom corner of the large chip on the right side of the board.

Version: 19.1.8 through auto update. Thanks.

//Solved.
« Last Edit: October 14, 2019, 02:55:29 am by blueskull »
 

Offline T3sl4co1l

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Re: [Solved] Cannot route on middle layers
« Reply #1 on: October 14, 2019, 03:22:51 am »
"Everything" including design rules?  Classes?

That's one thing that can be propagated poorly from SCH, classes.  Obviously the PCB-exclusive classes, but I've seen net classes not sync correctly.

Could also just be general paranoia, restart Altium etc.  Who knows. :-//

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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