I created a 4L design, which I started from top and bottom.
Today I was working on its middle layers, and Altium threw errors on clearance violation, which I didn't.
File is attached, if anyone can take a look at it.
The trace under investigation is 1V0 on the left bottom corner of the large chip on the right side of the board.
Version: 19.1.8 through auto update. Thanks.
//Solved.