Hello
I have been given 4 separate PCB designs and have been asked to combine them all into a single panel, which I've done using the Embedded Board Array/Panelize option.
My problem is when I generate a pick & place file since some of the individual boards use the same designators (e.g. LD1 & P1 are repeated twice) this makes setting up for production a bit harder.
With that said would anyone know a way around this problem? I was told that a long time ago Altium/Protel handled this very cleanly, but in the more recent versions the feature seems to have been lost.
Cheers