Electronics > Altium Designer

"Duplicate Net Names" error, despite nets on different children in heirarchical

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frogblender:
I have a heirarcal schematic:  top.schDoc,  and her two children, red and yellow.SchDoc.   

The "Net Identifier Scope" is, I swear (see pic) set to Hierarchical.

Yet upon compile, I get "Duplicate Net Names Wire" errors.

I'm missing something fundamental here... despite nets on red and yellow having the same name... the fact that red and yellow are children and the project is heirarchical, shouldn't those nets be isolated?

Any help would be greatly appreciated.

Pseudobyte:
zip up and attach your project

PlainName:
Shouldn't the net end in a port if it's connected elsewhere on the sheet?

Pseudobyte:
I think the issue here is you are not actually doing any hierarchical design. If you look at Altium's documentation this may be treated as a flat design if your top sheet does not have any circuitry or vertical connectivity. Your compiling strict hierarchical which makes me unsure if this is actually the issue. Make some fake ports and connect them between the sheets.

The other thing that confuses me is that you have two sheets with the same circuit. In a hierarchical/multi-channel design you would have one sheet with the circuit and make two sheet symbols on your top sheet one with designator red and the other yellow. When you compile, the original design (logical) spawns two physical circuits. You can change the behavior of how the compiled sheets are annotated from the logical schematic.

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