Author Topic: Embedded Board Array (PCB Panelization) - Correct way with AD20  (Read 686 times)

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Offline davide6893

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Hello to the whole forum,
I am designing some PCB boards and I would like to ask you some advice regarding the most correct method to perform the panelization with Altium.

In practice I would have 8 projects complete with different boards and I would like to make a single panel. I understand how to panel multiple boards of the same project, it is quite simple because the properties panel allows you to intuitively set the number of boards per row and column and the margins between each boards. On the other hand, as far as the tiling between different boards is concerned, I have not found a very effective method, if not that of positioning them manually and of distancing them approximately by measuring the distance between each one. This method does not seem to me very precise and effective, especially if corrections are to be made later. I would therefore like to ask if you know any more relevant techniques for doing this.

My boards also include special strings containing some parameters of the project and I would like to point out that from what I noticed they are correctly interpreted only if the respective projects are open at the same time, otherwise they are not converted.

Also some of my pcb make use of footprints that have some primitives (traces on silkscreen layer and mounting holes) that come out from the board outline. This isn't a big deal for me as the board size has already been calculated and all the relevant elements of the components are inside the board. However I would like to make sure that all the primitives that come out from the edge are discarded and that they do not create confusion for the producer who could misinterpret the actual size of the board. I don't want to modify the single footprint, because it is already correctly defined and I can use it later for other projects. Therefore, I would like to ask you which is the most correct method to do what I ask, specifying that the board border has been defined both as a board outline layer and as a keep-out layer.

The main problem I encountered when I created the panel with all the boards is that the primitives (traces on silkscreen layer and mounting holes) that come out of some boards are superimposed on other boards and this I would really like to avoid. I also noticed that some details are missing in the panel view which are then generated in the gerber files. That is, the dimensions of each individual board and the tables with the holes that I created for each board on the drill drawings layer are shown in the gerber of the complete panel, all superimposed on each other. I would like to avoid this thing if possible without modifying the design of the single board, however, because it must be in its own right and include only the dimensions and the table of the entire panel.

I attach some images that highlight the problem described.

I thank in advance all those who will give me a hand.
 

Offline SerieZ

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #1 on: June 03, 2020, 10:26:13 am »
Have you asked your Manufacturer to do the Panelization for you?
Is it really Critical for you to do it yourself? I usually work closely together with the Fabricant.

If you HAVE to do it yourself:
1. Read this:
https://www.altium.com/documentation/altium-designer/pcb-obj-embeddedboardarrayembedded-board-array-ad

2. Make a new Project and set up the Layers exactly like the other Boards. Place all the Boards into that project (Place -> Embedded Board Array).
If everything is compatible you can hide the Mechanical layers which mess with your other Boards and work like you would with a regular PCB.

:-// Honestly I find doing multiboard Panelization a mess in Altium unless you had the hindsight in doing the designs for it beforehand.
As easy as paint by number.
 
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Offline davide6893

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #2 on: June 03, 2020, 11:01:18 am »
Have you asked your Manufacturer to do the Panelization for you?
Is it really Critical for you to do it yourself? I usually work closely together with the Fabricant.

If you HAVE to do it yourself:
1. Read this:
https://www.altium.com/documentation/altium-designer/pcb-obj-embeddedboardarrayembedded-board-array-ad

2. Make a new Project and set up the Layers exactly like the other Boards. Place all the Boards into that project (Place -> Embedded Board Array).
If everything is compatible you can hide the Mechanical layers which mess with your other Boards and work like you would with a regular PCB.

:-// Honestly I find doing multiboard Panelization a mess in Altium unless you had the hindsight in doing the designs for it beforehand.

Thanks for the reply.
I should have JLCPcb to produce the pcb. These are prototypes and simple adapters and assembly will be manual.
I have been advised to make the panel because it was more convenient, but I'm not very sure. I can't choose to have the manufacturer make the paneling because they are different projects.
However, the panel's Altium project is already ready and with great effort with the correct distances, but I have doubts on how to proceed. I drew a V-cut line and the route path for milling for the remaining boards that could not be aligned correctly. There are also the "mouse bites" for the subsequent simplified depanelization.

I know how to proceed to make a panel with Altium, I also provisionally solved the problem of overlapping primitives and silkscreen lines by unlocking the footprint from the pcb project and cutting the tracks that came out with the "slice tracks" command , but if possible in the future I would like to avoid going to modify the board to adapt it to the panel.
The problem I have now is that during the gerber generation the mechanical layers of the individual boards overlap and in particular the dimensions and the drill tables of the individual boards between them, both on the driil drawings layer. Do you know any solution for this, without having to modify the single pcb board?
 

Offline SerieZ

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #3 on: June 03, 2020, 11:08:46 am »
Yeah I figure for Prototypes and small runs it is not that easy to get them to do it for you....

I would exclude all those offending Mechanical layers from Gerber Creation and make a new one only for the Panel.
I do not really see an easy workaround.
As easy as paint by number.
 

Offline davide6893

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #4 on: June 03, 2020, 11:20:27 am »
Yes, from the creation of the panel gerber I should exclude some layers from the individual tabs, but it only allows me for the panel layers and carries the existing ones of the individual boards without being able to disable them. In practice, if I have the drill tables on the same drill drawings layer for the individual boards and the panel, they all overlap (see "Panel Gerber - drilling table primitive overlapping.png" in the original post).
 

Offline free_electron

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #5 on: June 03, 2020, 11:21:29 am »
That .. doesn't work that way ...

Panelisation is basically an array (step and repeat) of the same board. What you are doing is a 'mixture of boards'.

There is a difference you may not realize and it has nothing to do with your design but everything with the manufacturability.

- you cannot provide a master netlist. You will have duplicate designators. This is problematic for the testers during production. There are ways to import multiple designs onto one panel but that is done using a Gerber editor. Altium has no such capability ( Neither have any of the other pcb tools !) This is specialized work and required the fab tools like Ucam , Genesis 2000 , Valor and others  . You can not do that because it is machine and process dependent.
- you can not create a master pick and place file... because you have duplicate designators and because you have rotational/positional offsets between various boards. The machines cannot handle this. yes you could write  parser and spend time creating a 'merged file' but this is tedious. A true array spits out one pick and place file for 1 board , and a list of 'zero' coordinates. The pick file is identical for all boards. Just the origin changes. the pick and place robot then applies an offset to the pick file to cover each step and repeat. The reason behind this is to perform placing optimisation. The machine preprocessors will not place board1 , then board 2, then board 3 . They will place all 10k resistors first. they want the minimum amount of travel and reel/ head changes. the machines also keep track of how much parts have been used per feeder and will switch to a different part while the operator swaps a reel. the machine does not stop waiting for more 10k resistors. It goes on with the next part while the operator swaps the reel.

What you are trying to do is to make a 'breakable' board. you have to treat this entire desig as 1 board , 1 design , 1 schematic.  The machines do not know , neither in production nor assembly. They don't care about the routing lines or cut lines.
You have no duplicate designators and you have one unified netlist.

So , to do that in altium : you create a multiboard design ( possible in AD20 ). You can then create the panelisation in Draftsman. You do not place drill tables or any other documention in the pcbdoc files. The pcbdoc only contains the board. Draftsman is then used to add all the other elements.


Or, the simpler way without too much of a learning curve:

you make a new project, add all your existing design files to it.
make sure you have no shared netnames between 'boards sections'
So all the grounds of board 1 are called GND1. all the grounds of board 2 are called GND2 and so on. In your project settings you can specify how designators are to be handled. Apply a prefix to the designators or an offset per page. problem solved . That's what that is for.
You create the paneled design as a single pcbdoc file. that design can then itself be further stepped and rotated on a larger panel.  You have the advantage that you can design additional things like manufacturing rails and other items. you are in control.

This has been done like ... forever. Take apart something like a home theatre amplifier from sony or onkyo. they have like 5 or 6 boards in them. You will see that these boards are laid out attached to each other using mousebites. The entire board is soldered in one shot and 'cracked' the moment it goes into the enclosure. They even stuff the wiring across the boards on there prior to soldering. Sometimes they even use 'empty space' in such a panel as mounting elements or wiring guides. This would normally be waste material but they use it as a clip or clamp to hold other things down. you will see that designators on one board are in one range ( 1000 to 1999 ) another board os 2xxx , another is 3xxx  or P1Rxxxx P2RxxxX P1Cxxxx P2Cxxx and so on.

« Last Edit: June 03, 2020, 11:23:24 am by free_electron »
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Offline davide6893

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #6 on: June 03, 2020, 11:48:10 am »
Quote
That .. doesn't work that way ...

Panelisation is basically an array (step and repeat) of the same board. What you are doing is a 'mixture of boards'.

There is a difference you may not realize and it has nothing to do with your design but everything with the manufacturability.

- you cannot provide a master netlist. You will have duplicate designators. This is problematic for the testers during production. There are ways to import multiple designs onto one panel but that is done using a Gerber editor. Altium has no such capability ( Neither have any of the other pcb tools !) This is specialized work and required the fab tools like Ucam , Genesis 2000 , Valor and others  . You can not do that because it is machine and process dependent.
- you can not create a master pick and place file... because you have duplicate designators and because you have rotational/positional offsets between various boards. The machines cannot handle this. yes you could write  parser and spend time creating a 'merged file' but this is tedious. A true array spits out one pick and place file for 1 board , and a list of 'zero' coordinates. The pick file is identical for all boards. Just the origin changes. the pick and place robot then applies an offset to the pick file to cover each step and repeat. The reason behind this is to perform placing optimisation. The machine preprocessors will not place board1 , then board 2, then board 3 . They will place all 10k resistors first. they want the minimum amount of travel and reel/ head changes. the machines also keep track of how much parts have been used per feeder and will switch to a different part while the operator swaps a reel. the machine does not stop waiting for more 10k resistors. It goes on with the next part while the operator swaps the reel.

What you are trying to do is to make a 'breakable' board. you have to treat this entire desig as 1 board , 1 design , 1 schematic.  The machines do not know , neither in production nor assembly. They don't care about the routing lines or cut lines.
You have no duplicate designators and you have one unified netlist.

So , to do that in altium : you create a multiboard design ( possible in AD20 ). You can then create the panelisation in Draftsman. You do not place drill tables or any other documention in the pcbdoc files. The pcbdoc only contains the board. Draftsman is then used to add all the other elements.

Thanks for the exhaustive reply and details on mass production.

As already specified, these are amateur prototypes, they will not have to be mass-produced and will be assembled and soldered by hand. I have different individual projects which I then put them together in the separate panel. Obviously in the panel there are duplicate designators deriving from the different cards. I decided to make the panel to minimize costs, but I'm not sure it was a right choice.

Quote
Or, the simpler way without too much of a learning curve:

you make a new project, add all your existing design files to it.
make sure you have no shared netnames between 'boards sections'
So all the grounds of board 1 are called GND1. all the grounds of board 2 are called GND2 and so on. In your project settings you can specify how designators are to be handled. Apply a prefix to the designators or an offset per page. problem solved . That's what that is for.
You create the paneled design as a single pcbdoc file. that design can then itself be further stepped and rotated on a larger panel.  You have the advantage that you can design additional things like manufacturing rails and other items. you are in control.

This has been done like ... forever. Take apart something like a home theatre amplifier from sony or onkyo. they have like 5 or 6 boards in them. You will see that these boards are laid out attached to each other using mousebites. The entire board is soldered in one shot and 'cracked' the moment it goes into the enclosure. They even stuff the wiring across the boards on there prior to soldering. Sometimes they even use 'empty space' in such a panel as mounting elements or wiring guides. This would normally be waste material but they use it as a clip or clamp to hold other things down. you will see that designators on one board are in one range ( 1000 to 1999 ) another board os 2xxx , another is 3xxx  or P1Rxxxx P2RxxxX P1Cxxxx P2Cxxx and so on.

I would not like to go over and overhaul the individual projects that have been completed.
 

Offline free_electron

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #7 on: June 03, 2020, 12:04:36 pm »
have each board made individually. done.
what you are trying to do is mass production optimisation. that is useless for a one-off prototype...

You don't have the tools (you need gerber maipulation tools, and no , camtastic in altium is NOT such a tool ! i am talking the software that can inject the mousebites, scoring, rails, and other manufacturing items. that is highly specialized stuff. They literally do that in a few mouseclicks. your boards are loaded in as blocks and they place these blocks according to design rules, think of it this way : your components are a 'board'. just like you have component to component rules, they have board to board rules. It's like they would make a library containing your boards. they simply place and rotate. just like you place tracks or split planes  they place routing channels and v-scores. the whole thing then gets a border slapped on with a lot number, barcoding , coupons , panel grids and whatnot.
just like you make a gird of your boards , they then make a grid of this assembly. ( typically panels in the pcb world are 18 by 24 , so your 'mulitboard grid' will itself end up being stepped and repeated on a real panel ...


heh... here's an idea. create a new pcb library. store one board as a single component in that library. ...  ( you can copy from pcb to library, i do that all the time )
now you have a 'library' of sub-boards ....
ake a new board and 'place' those library-ized boards. you can now easily move them as blocks and create the other stuff.

worth a try ...
and if you place the drill table on that master board all will resolve nicely ...



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Offline SerieZ

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #8 on: June 03, 2020, 12:50:38 pm »
All this opens the question to me of how do PCB Manufacturers solve Pooling (cheapest prototype boards are already produced as multiboards) and brings me back to: Ask the Manufacturer what he can do for you (if cost is your Problem as well).
I really see not why you would want to punish yourself with this task.

Really good Post from free_electron BTW
As easy as paint by number.
 

Offline Pseudobyte

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #9 on: June 03, 2020, 02:58:20 pm »
I have always subscribed to the methodology that you let the fab house step and repeat the data. If you want to dictate your panel configuration then you draw it in a fabrication drawing.
“They Don’t Think It Be Like It Is, But It Do”
 

Offline free_electron

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #10 on: June 03, 2020, 03:50:49 pm »
All this opens the question to me of how do PCB Manufacturers solve Pooling (cheapest prototype boards are already produced as multiboards) and brings me back to: Ask the Manufacturer what he can do for you (if cost is your Problem as well).
I really see not why you would want to punish yourself with this task.

Really good Post from free_electron BTW

They solve pooling using either Fontline or ucam or the other fab tools.

You literally have to imagine it as a 'higher level' layout tool. just like we place components from a library ( a component is nothing but a collection of lines , pads and holes. . a board is a collection of components with additional lines pads and holes. ) they place boards.
So all the boards that we make are 'components' for them. they drop , rotate and shift these. the tool knows the design rules for the panel , in the sense , it knows how much milling space is required between boards. it knows how much the individual boards need to be kept away from the panel border ( they too need a border for the machines to grab the panel and the ink to run out. that is 'wasted space' but required for the machinery. there are registration holes for the machines and whatnot. in that border they also put impedance control coupons , alignment marks and a whole bunch of other fuff that pcb designer do not need, but they need for the production process quality and process control.

So they manipule whole board designs just like we manipulate components. Want mouse bites ? just like we have a trace router , they have a 'border router'. they draw the border and that tool automatically drops mousebites with the right distance between them so that the panel does not crack too easily , the bites autospace and autocenter on edges. castellations ? same thing. Those tools handle that in a few clicks.

you cannot do this as a pcb designer becasue you need to know the production process. are they going to use liquid ink or dryfilm ? what will be scored, what will be milled, what size router bit are we using. all those 'manufacturing rules' are driven by the in house machinery. pcb designers design a board and can send it into any fab out there. but the 'processed' data becomes fab speciic. you can not take those panel files and go to another fab. it may not work as the machinery is different.

They do even more than that. dpeending on foil thickness they actually oversize the traces we design to end up with the correct trace width. they drill larger than what we specify becasue what we specify is the end size they need ot account for plating thickness.
soldermask openings are adjusted depending on ink viscosity.

none of that matters for the board designer as it is fab specific , but it is not portable between fabs. even if those fabs belong to the same company ! this board ? only for that fab, we can;t run it in the other fab due to machine differences. if we can run it even then the 'fab' data is different. i have seen many times that a board got qualified , they changed fabs and there were issues. even though both fabs are own by the same company !


in the end : you can not do panelisation beyond simple step and repeat. And even then : leav it to the fab house. you may not know the criteria for milling channels . You'd think let's mill these boards out. nope. you need corner retaining or the completely milled boards go flying or shifting during the milling of the rest. if that bit backtracks over an already milled channel it will run straight through an already milled board. ( yes they have vacuum tables , but the risk still exists with small boards that fall between suction nozzles )

dont do it. it is a waste of your time.

if you absolutely must have a 'one panel' like for what they do in cheap audio equipment where they crack the boards post-assembly, then you need to design this entire thing as 1 board. but even then there are rules. Such boards are typically phenolic paper, single sided and smt bottom , thru hole top.  it saves a lot of time on the pick and place line. you only need 1 line per whole product ( if a product has 5 sub boards you would need 5 different assembly lines the conveyer needs ot be adjust to the size of each sub board. and if the boards are non rectangular each board needs rails to fir the conveyer. that is waste of material and money. make a panel add rails to the panel. assemble the whole thing on one line then crack the assembly , put the main board in the bottom of the case, the frontpanel board in the front , the amplifier connector board int he back, a piece of the board with no parts gets hand soldered on the transformer , etc etc etc.

but that approach is done be designing the entire thing as 1 schematic place and route on one board. it is not done post layout. it is part of the layout.

There is so much about this stuff that people don't realize.. i had been making boards for 23 years professionally ( using fabs) and 8 years at home before that. Then i switched and became full time entrenched in board design and realized : i don't know jack-shit about this stuff... because i had only made rectangular boards...

Start designing boards that need to fit somewhere constrained. odd shapes , keep space between big electrolytic caps so they can apply hot snot to glue them. leave space for selective soldering or conformal coating ( that liquid needs to be kept away from connectors at it wicks in there due to capillary effects ruining the connectors. ) high currents, heavy copper ( 4 or 6 oz copper foils) . boards that do 300 400 ampere, reinforced busbars. Boards for radar at 76 GHz. Boards that run DDR4 at 3.6Ghz , blind, buried, stacked vias , plugged vias, flex-rigid-flex. And then optimize them for assembly speed and reduction of waste material ...

Soldermask ? that is no longer done the way you think . take a look at this :



or



That mask is DRY when it comes out of the machine. and that video is real-time, not sped-up.

Traditional masking is : paint the board with wet ink. let it dry , expose to a film or to a direct-imager. this hardens the ink. then wash away the uncured ink.
drying, time , wasted ink , ink going where you don't want it ( in the holes )

This inkjet machine ? the ink is liquid when it prints , but the inkhead also has a ultraviolet lamp that hardens the ink instantly. the moment the drop hits the panel it is semi-hard. there is only a post-print full cure step required.
Registration and trace widths are possible that you cannot do optically.

bUt .. do you think your local shop has those ? nope. these machines are so expensive they can only be afforded in mega-fabs in the far east. your local shop is still a paint-based shop.

oh, and they spray 2 colors at a time. Soldermask AND silkscreen in one shot !

You may be aware about optical inspection to find shorts and opens in a board .. but , did you know they are now repaired ? They laser cut shorts, and the laser engrave new copper !



And those machines are wickedly fast !



this thing is eye-watering ...




« Last Edit: June 03, 2020, 04:16:43 pm by free_electron »
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Offline davide6893

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Re: Embedded Board Array (PCB Panelization) - Correct way with AD20
« Reply #11 on: June 08, 2020, 09:56:32 am »
The manufacturer (JLCPcb) advises me to have the PCBs produced as a single panel (mixture of board) for the different designs with connection and stamp holes between with designs because the price is lower. However, from a first analysis I saw that placing the individual orders the price is cheaper and the simpler procedure. In the case of the panel, on the other hand, I have not received any indications to correctly position the cards and decide the route path and the mouse bites to separate them. I should therefore follow their declarations of limits and clearances to correctly draw the panel by myself (attachments in the first post).
 


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