changing component without me asking it to.

[Lyndsay_Doyle]

I upgraded to AD22 from AD21.
I am adding in a couple of components for some ESD chips.
I added the components but wondered why I now have over 500 DRC errors, when I laid this out last week in AD21, I had zero.
Investigating further when I did update to PCB design, it was telling me that I had to remove a pin from a capacitor.
Cross probing revealed this (see Changed components picture) on the my processor circuit diagram.
See original picture as it was before the change from AD21 to AD22.
Look also what it has done to the resistors. The have all gone to a default value of 1k and default symbol.
The caps were 18pF placed horizontally, now changed to 100pF placed vertically.
God knows where else this has happened.
Basically this design is now screwed up.
This has happened because I went from AD21,  to AD22.
Now this. Could this tool be any worse?
More time wasted.
Why has this happened and how do I fix this?
Any help gratefully recieved.

[PlainName]

Sorry, can't help with this but just to note I upgraded 21 to 22 mid-design and don't recall any similar issue occurring. Not saying it's not buggy, but whatever caused this is probably a bit of an edge case.

Can you take the unmodified design and push to PCB before adding the ESD stuff? That way it would ensure the PCB and schematic are in sync before making changed.

[Lyndsay_Doyle]

Thanks for your reply.
I have been extreemly lucky here.
Aside from wasting all morning trying to fathom out what happened, I did have a zipped up backup version in my folder.
Lucky me right?
I have now unzipped and saved that in my folder, back to square 1.
I have opened in AD21, and it's good, without my ESD chips in of course.
Why did it do it? Must be yet another bug, Good grief.
I am seriously considering proposing to my diresctor to ditch this and look at another tool.
That is a gamble of course, PADs, eCadstar, Cadence etc. may also have some annoying bugs that I dont know about and be just as bad.
I'm still not happy though.

[PlainName]

I did have a zipped up backup version in my folder.
Lucky me right?

Yes, lucky. Perhaps you could take steps to remove such luck, though. For instance, I use AJC Active Backup (alternative tools available) to make a backup copy of anything in a particular folder hierarchy whenever it's changed (actually written to disk), which it does entirely in the background without fuss. Indeed, I have sometimes forgotten it's doing this and spent time retrieving a file from normal backup media when it would have been quicker, simpler and more focused on exact change to retrieve from AJC

[ajb]

Yikes!  What is your library setup?  Can you try opening the backup project in AD22 and see if you can replicate the problem?

Altium caches component data in the project, so it really should never change components, symbols, or parameters without an explicit update action of some sort.  The fact that C1/C2 rotated, and the resistor symbols have different parameters visible suggests to me that the components were updated from the library with different symbols.  Are you quite sure you didn't do any sort of update from libraries at some point?  If the new version has different libraries (or different library paths) configured, I could see that causing this effect, but again, that would generally have to be a manual update to replace the internal copies of those symbols. 

[Lyndsay_Doyle]

Hi ajb,
I cant be certain what happened, only that I updated from 21 to 22. Maybe there was something during this process that said update from library?
My library as far as symbols is comcerned is small when it comes to discretes, resitor, one symbol, caps two symbols, NP and P, inductor, two symbols, normal coil and a Common mode coil. That's about it.
Why would this result in all of my resistors reverting to a 1k default, the caps reverting to 100pF and drawn vertically? Even if I did update from library, why would it change anyway?
I am confused and not at all happy with the stupid things altium does on occasion.
Maybe it is me because I am a stupid chartered Engineer.