Polygon pours on internal layers

[Posh]

Hey all,

I have been struggling for a few hours to get polygon pours to appear on the internal layers of my four layer PCB.
Polygon pours are working perfectly on the external (top and bottom) layers, and I can see the copper in 3D mode.
On internal layers, the polygons will not fill when within the board region - and the copper does not appear in 3D.
If I move the polygon on an internal layer to outside of the board region, It will pour just fine...

I have considered using 'plane' internal layers, but would prefer to stick with signal layers for their flexibility. My layer stack-up settings are in the image.

I'm pretty stumped by this - any advice would be appreciated!

[pigrew]

Some ideas that come to mind:

• There are no existing objects on the inner layers on the particular net, and you asked it to "remove dead copper" in the properties of the polygon.
• In the design rules, the board edge clearance is set very high (wider than your board's size), so the polygon is illegal.
• Polygon net is set to "None".

A lot of the options can be set in the Polygon Manager. Perhaps post a screenshot of that, showing the properties of the polygon that's at fault?

[Posh]

Thanks for the ideas, I've attached an image of the Polygon Manager

I haven't added any objects to the inner layers - there are only the multi-layer vias and through-hole pins.

My polygon edge clearance is 0.25 mm, which seems to be working on the external layers.

My polygon net in this example is set to GND, the other two polygons I am working with have their respective nets.

[Psi]

Do you have power/ground available on the inner layer for the polygon to pour from?
It wont pour if there's nothing to pour from.

Also check that you don't have some weird polygon clearance rule that keeps it from getting close enough to GND vias to connect to them.

You will get problems if you have GND on the internal layer but the polygon pour cant get close enough to touch it due to a rule.


As a test, disable the "remove dead copper" tickbox for the polygon pour and re-pour it.
See if you get copper on inner layers then.
The problem may become obvious, like the polygon might be avoiding touching your GND via and so is dead copper and being removed. etc..

[Posh]

I should have power/GND to pour from, as I have ground pins/vias on the ground net coming through the layer - Just in case I dont, I added a GND pad to the layer.

I checked the PlaneConnect, PlaneClearance and PolygonConnect rules - I don't see anything out of shape, and these rules work fine for pouring on the external layers.

I've been testing with 'remove dead copper' checked and unchecked without change.

Attached is a screenshot showing the GND polygon and the nets available.

[T3sl4co1l]

Is auto repour disabled?  You've been manually repouring, right?

Tim

[Psi]

If you want to post/PM your files i will have a look

[Posh]

Is auto repour disabled?  You've been manually repouring, right?

I've been manually repouring with 'Repour Selected' or 'Repour All'

If you want to post/PM your files i will have a look

I don't mind PM-ing them, i'll send them through in a few hours

Thanks for the help guys

[tszaboo]

If you dont have traces on the inner layers, then use the inner layers as planes. Lot simpler. It works in inverse.
Only use signal layers for the inner layer, if you really really run out of space on the top and bottom.

[Psi]

I prefer all signal layers.  Power planes can get annoying when pcb houses have to deal with inverted layers.

The OP should be able to work with polygon pours on the inner layers exactly the same as the outer layers.

[T3sl4co1l]

In fact I did a design recently, 8 layers ~1k components, and the constant recalculating inner planes when moving any hole/via/pad was disgusting (~2 sec).  Changed to polygons, no problems.  I mean, repour is even slower (a minute), but that's done in batch, much more tolerable.

Tim

[langwadt]

I prefer all signal layers.  Power planes can get annoying when pcb houses have to deal with inverted layers.

The OP should be able to work with polygon pours on the inner layers exactly the same as the outer layers.

what really the point of using power planes any more? it's not like making it easy to do with tape is something that
has been a concern for the last many decades

[Psi]

I prefer all signal layers.  Power planes can get annoying when pcb houses have to deal with inverted layers.

The OP should be able to work with polygon pours on the inner layers exactly the same as the outer layers.

what really the point of using power planes any more? it's not like making it easy to do with tape is something that
has been a concern for the last many decades

exactly

[Posh]

After my friend and I played around with the board for a few hours, we finally got it to work!

The issue was quite obscure - The layer stack manager had multiple 'Board Layer Stack' configurations, which seemed to be conflicting with one-another. After removing the duplicates everything pours fine.

I am not sure how these duplicates appeared, I'd never even seen this drop-down before... to make it appear you have to enable 'Rigid/Flex' under the 'Features' drop-down. From there you can delete the duplicates by selecting them and then clicking the bin.
Certainly a frustrating issue to troubleshoot!

Thanks for the help

[tszaboo]

I prefer all signal layers.  Power planes can get annoying when pcb houses have to deal with inverted layers.

The OP should be able to work with polygon pours on the inner layers exactly the same as the outer layers.

what really the point of using power planes any more? it's not like making it easy to do with tape is something that
has been a concern for the last many decades

That you double click on a layer, and set it to be a net, and you are done with it. If you polygon pour it, you have to babysit the layer with repoiring it continuously, set via connection styles and so on. It is just so much easier. If you have a large board, repour can also take serious amount of time.
And I never seen a PCB manufacturer, who didnt immediately realised when they saw a plane. Besides, you send a stackup legend, so define it if you really need to.

[Psi]

I prefer all signal layers.  Power planes can get annoying when pcb houses have to deal with inverted layers.

The OP should be able to work with polygon pours on the inner layers exactly the same as the outer layers.

what really the point of using power planes any more? it's not like making it easy to do with tape is something that
has been a concern for the last many decades

That you double click on a layer, and set it to be a net, and you are done with it. If you polygon pour it, you have to babysit the layer with repoiring it continuously, set via connection styles and so on. It is just so much easier. If you have a large board, repour can also take serious amount of time.
And I never seen a PCB manufacturer, who didnt immediately realised when they saw a plane. Besides, you send a stackup legend, so define it if you really need to.

Yes that's true.
If you're doing a large 8+ layer pcb i can imagine the re-pour time would be longer.
But time to pour a polygon layer is proportional to how complex the layer is.  A layer with nothing on it expect the polygon fill should re-pour pretty fast.

[thm_w]

Join the pleb world, for people without supercomputers we shelve polygon pours to avoid recalculating until you are close to finishing the layout.

btw, you can define the PCB shape in the keepout layer then no wild polygon shapes are needed to match the board (just make a big oversize square). But not much of an advantage until you are re-sizing/re-drawing the board shape.

[Pseudobyte]

btw, you can define the PCB shape in the keepout layer then no wild polygon shapes are needed to match the board (just make a big oversize square). But not much of an advantage until you are re-sizing/re-drawing the board shape.

Or in the polygon manager you can create a new polygon from the board shape

[Psi]

btw, you can define the PCB shape in the keepout layer then no wild polygon shapes are needed to match the board (just make a big oversize square). But not much of an advantage until you are re-sizing/re-drawing the board shape.

Or in the polygon manager you can create a new polygon from the board shape

yes, if you don't know about this, learn about it now.
So much easier.

[ajb]

btw, you can define the PCB shape in the keepout layer then no wild polygon shapes are needed to match the board (just make a big oversize square).

Or just enable a Board Outline Clearance rule (under manufacturing rules).  I think that rule became available in AD17 or AD18?  That works from the actual board outline definition, so it always responds to changes in board shape (including board cutouts), with no need for any keepout primitives.

[thm_w]

Or just enable a Board Outline Clearance rule (under manufacturing rules).  I think that rule became available in AD17 or AD18?  That works from the actual board outline definition, so it always responds to changes in board shape (including board cutouts), with no need for any keepout primitives.

OK thats definitely the way to go, it seemed like they were deprecating keepouts as they are difficult to work with now. thanks.