Help me translate JLCPBC capabilities to Altium design rules

[Piachnp]

Hello, this is my first time posting in the forum. I am building a very small board (a hexagon shape inscribed in a 25mm diameter) and to make routing easier it is important that I use the tightest clearances possible. So I went to JLCPBC capabilities page (https://jlcpcb.com/capabilities/pcb-capabilities) and try to set the correct design rules in Altium Designer (created the project with the old rules, not the new constraints feature which I could not understand or navigate as easily). I'm having some trouble and wanted to some help to verify that I am doing the clearance matrix correctly:

• Hole to hole clearance(Different nets): 0.5mm >> Altium shows "Hole" as a row but there is no column, so doesn't seem like I can do this one?
• Via to Via clearance(Same nets) : 0.256mm >> Altium matrix is for different nets so not sure how to do this one. I can enforce this myself pretty easy for same nets. But what do I use for Via to Via when they are different nets? This is an important rule for my design and I'm lost what to put in the via vs via cell of the matrix. Or does the 0.5mm Hole to hole clearance from the item above apply here? This is what I am using now, and its really bothering me so it would be great if I can lower it...
• PTH to Track: 0.33mm && NPTH to Track: 0.256mm >> My board is 2 layers, so isn't a PTH the same functionally as a via in my case? The Via to Track capability is 0.254mm. Also Altium has a Hole vs Track cell.. should I set this to 0.33 or 0.256mm?
• Pad to Track: 0.2mm >> Do I set here both SMD and TH Pads ? What about the Copper vs Track cell? should that one too be 0.2mm ?

I have attached here an image to show my clearances the way the stand right now. Let me know if they make sense against the JLCPBC link I shared.

Thanks in advance for your help!
Pedro

[jc101]

JLCPCB do publish Altium rules and some layer stackups -> https://jlcpcb.com/help/article/8-How-to-export-Altium-PCB-to-gerber-files

I've used these before with no issue.  If nothing else, they would be a handy comparison.

The new constraints manager is a pain; you cannot share any project created with anyone not on a Pro subscription.  It should be disabled by default.

[PlainName]

Via to Via clearance(Same nets) : 0.256mm >> Altium matrix is for different nets so not sure how to do this one.

You can duplicate that clearance rule (or create a new one) and then select 'All nets' or 'Same net only' for the matrix, then change the clearances as appropriate. Generally, if the text is blue you can click on it and change it.

[Piachnp]

Thank you both for the replies! I did download the rules file you mentioned and compared and found that almost the full matrix was set to 0.203mm... which I suspect is not correct. Since the biggest constraint for my design was the via to via distance I contacted JLCPBC support and they said to use >=0.5mm which is what I already had...

I suspect violating these rules will not always yield defective boards, but it might (hence why many people say using those rules works just fine). I suppose it all depends how well calibrated their machines are in terms of making holes. As they get closer to the top end of their advertised tolerances, designs that violate their rules might start yielding bad boards? 

[PlainName]

The rules are what they guarantee. If you break them by a little bit it may well work, but you can't complain if it doesn't. But it also depends on what rule you're breaking - solder mask sliver or silkscreen clearance, for example, are usually just cosmetic issues if they fail on prototypes but might otherwise be significant problems.

[thm_w]

I suspect violating these rules will not always yield defective boards, but it might (hence why many people say using those rules works just fine). I suppose it all depends how well calibrated their machines are in terms of making holes. As they get closer to the top end of their advertised tolerances, designs that violate their rules might start yielding bad boards? 

If you clearly break the rules they will either:
- modify your design to fit within the rules and not tell you
- reject your design

Its unlikely you'd ever get a bad board directly due to submitting a tolerance that is too small.