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Hierarchical Design, some nets are not connected

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hitech95:
Ok, looks like that now the connectors are connected but the address selection resistors are still not connected. Are the busses global?
This also happends on the in sheed net class PRSNT#, when compiling it says that nets are duplicates.
Thi snet is only inside child sheets, it does not have ports or harnesses.

Why the hell are the nets in some way global?
This is starting to make even less sense.

Removing net names and only using wires is a no go. the project you have is really simplified, in the original design all those nets are connected, there are net classes, directives, etc.
Each sheet have distinct blocks with descriptions.

looks like that altium is not appling the suffixes on the child nets names

The only way is to enable sheet number, but having rooms name as prefix/postfix would be lot better.

ajb:
I can't really see the connectivity issues with the PRSNT nets because of the footprint errors, but I would guess, at least in the test project, that it's because those nets go to ports without any further connection, and are again ending up with duplicate names during the initial netlist creation which causes Altium to give up.  However, if this is a problem in your larger project, then I have no idea because there's more going on in that project and no one can see it unless the have access to that project.  But as a general rule, solve the footprint errors first, then if you still have problems try adjusting the names of the ports, nets, and harnesses, and be mindful of the limitations I mentioned previously.  Any net labels that use a scheme that fits into the patterns that Altium uses for creating net names in harnesses is liable to run into the same problems.

hitech95:
I have attacched another example project with the issue in details.

The file "ReDriver" is an example of the issue I'm facing. The nets are only connected on one side.
The annoing thing is that the connetor have a specific pinout and in reality it is another child sheet.

For what I can understand is that the issue is "Duplicate Nets Label" on two different child files.
AFIK Altium should add SheetSyblo prefix to the nets to prevent those issues.

What does you suggest?

The "fake" redriver circuit:

The broken harness:
 

frogblender:

--- Quote from: hitech95 on February 03, 2021, 04:15:27 pm ---I have attacched another example project with the issue in details.

The file "ReDriver" is an example of the issue I'm facing. The nets are only connected on one side.
The annoing thing is that the connetor have a specific pinout and in reality it is another child sheet.

For what I can understand is that the issue is "Duplicate Nets Label" on two different child files.
AFIK Altium should add SheetSyblo prefix to the nets to prevent those issues.

What does you suggest?

The "fake" redriver circuit:

The broken harness:
 

--- End quote ---

Hi hitech95...  did you ever solve the   ""Duplicate Nets Label" on two different child files."  problem???

I have the exact same issue.

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