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Hierarchical Design, some nets are not connected

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hitech95:
Hi,
I've started designing a new PCB, this time the project is a bit more complicated than usual,
Having a lot of busses, and connector and channels I've started digging into Hierarchical Design.

Now I'm facing issues even with the simplest desing.

Lets say I have 3 connectors with one I2S bus each (MCLK, BCLK, WS, SD)
Now lets say I have another connector that receive the three busses.

My project structure is:

* Overview
* Connector_MUX
* Connector_AFE1
* Connector_AFE2
* Connector_AFE3
The Connector_AFEX files have a Harnes connector called BUS_I2S_AFE. (The three inputs are basically the same thing)
The Connector_MUX file have the three Harnes (BUS_I2S_AFE) as inputs but with three different harness ports.

When I import the changes to the PCB not all the nets are connected, some headers have pins with correct net names, some other time they don't.
The issue is that this issue is creating me a lot of troubleshooting non-sensese. Especially when each import changes the netlist even if the schematic is unchanged.

What I'm I doing wrong?
In the atachments there is my simplified project.


dunkemhigh:
I am not seeing your problem. Maybe I'm not looking for the right thing, but an update to the PCB results in the three AFEx connectors having the same connections each time. The kind of problem you note might be caused by having global scope for net connections, but the project options look OK. Presumably your non-simple project has the same settings.

I note there are issues with missing connections in the schematic - could they be affecting things?

Pseudobyte:
Yeah, I am not seeing any issue either. Ratsnest looks correct. Can you give an example of a pin that has the missing connection or specific nets giving you issues?

hitech95:
This is the same project with the correct connectors, and some more ports, this one is failing (Randomly).
In this design I only changed AFE1 and AFE2, AFE3 is the same but it is also failing. Afe 2 Intead is correcly created.  |O

hitech95:
No,
I'm still tring to understand how to use this function  :-//
Starting to feel dumb.

For my protype board I will have to go with flat design at this point...
It will be a mess:

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