thick trace vs copper pour for power plane

[kikyw]

hello guys

I have a question about power rails on power plane.

I requested a small company to draw 4 layer artwork of my circuit and received the first drawing image attached below.
On the power plane, all the power rails are connected using only thick trace.
company man explained that it's better for noise reduction, lines affect signal line much smaller than copper pour do and
it's just for convenience to use copper pour.
is it reasonable? I have not seen any other practice using thick trace on power plane and even can not know if he is right.
(I am a mechanical engineering student)
I could not find any explanation or recommendation on this.

In summary, which one is better for noise reduction. thick trace or copper pour on power plane?


attahced
all powers originate from LDOs on the right side powered by battery
upper side for analog and bottom for digital
 power plane.png (198.43 kB. 2131x1422 - viewed 770 times.)

[T3sl4co1l]

Impossible to say without more information (schematic, other layers, and enough time to do a proper review of them).

I will say, they've done a quite pleasing job with the routing.  That attention to detail is often suggestive of other details like local bypassing and filtering, short and tight layout, keeping signals and power separated properly, etc.  But not at all assured, so, I can only guess at this.

The one thing that is true in general, is planes/pours have more capacitance to the ground plane, and far less inductance between points; often, it is reasonable to remove bypass caps in that case, because such a wide connection acts nearly like an ideal node.  Conversely, the lack of ideal connection between nodes, can also be of some value, when it is used as a filter structure; but this likely plays little role here, as the filtering value is up in the ~MHz typically, which might be above your analog bandwidth where it won't provide any value (but, again, depends, maybe this is radio-frequency stuff, I don't know).

And it might be more or less irrelevant, anyway, depending on what's being done.  For example, maybe crosstalk from digital to analog domains would introduce noise, but the amount is below the input threshold anyway (say, below the noise floor of a 10 or 12-bit ADC) so any additional effort is unnecessary.

Or maybe it's a high bandwidth 24-bit converter and the layout shown is actually insufficient.

There is one other small issue, of manufacturing: it is generally recommended to balance the density of copper placement on pairs of layers in the stackup.  Assuming the other inner layer is solid GND pour, then its pair (this inner layer) will be much lower density, and this can warp the board slightly.  Likewise the balance between top and bottom layers (which is usually fine between the components and traces placed on them).  This can be solved by the PCB fab house (permit placement of copper thieving), or is another point in favor of pours/planes.

Tim

[ANTALIFE]

First thought is no. I have not come across any example where thick traces are better than a copper pour/plane. And like T3sl4co1l said, would need to know more information about board before we can make an accurate judgement

For example, would like to know what the other 3 layers look like as well as the board stackup. As I suspect the current arrangement will have odd return paths which may lead to board misbehaving

[thm_w]

Why would there be odd return paths when the other internal layer is almost certainly a ground fill?

[ANTALIFE]

Why would there be odd return paths when the other internal layer is almost certainly a ground fill?

I am making a crude guess that the PWR layer OP posted is on layer 3. What I am worried about is components on layer 4, which would use layer 3 as their reference plane. The problem is that there is no continuous plane on layer 3 to reference to as all copper is just wide tracks

But again, won't know for sure till OP shares what other layers look like

[kikyw]

I am sorry for the late response.

hmm.. more detail...

As I mentioned, I am almost a newbie to electronics.
Until one year ago, the undergraduate class addressing Arduino and other basic stuff for mechanical engineering students is my all the experience on electronics.
Anyway, for those who might be interested in this post, I will do my best!

First of all, you can find my circuit attached below.
The circuit measures resistance change of MEMS fabricated calorimetric flow meter.
Each of the three resistors on the flow meter is connected(J6,7,8 or 9) in series with two digipot(AD5174, AD5252).
The resistor on the sensor and combination of two digipot compose Wheatstone bridge with resistor array(Y4485V..) for the opposite side. After matching the resistance of the sensor resistor and digipot array, the resistor is heated with a power of ~10mW and resistance change is measured using ADC(LTC2368-24). Each of resistance change of three resistors is captured one at a time under the control of analog switches(U24, U16) with an interval of ~1ms for the settling of filter right before ADC. Then, using some average scheme of four measurements of each resistor, I can get the resistance change of all at the same time point under the assumption of linear change of temperature of the resistor. During measurement, only CNV pin of ADC fluctuates with the rate of 1MHz until 8192 measurements(or more) are stacked for the integrated digital filter, so it takes ~9ms(8+1) to get the one measurement. I think these are enough to explain my circuit.

Artwork for this circuit is attached below as well.
Hmm.. for artwork, I have nothing to tell you guys much. the circuit design has been modified for more than a year, but every artwork is done by another person. The only thing I do for artwork is, after getting the first drawing, to call the company guy and ask about his concept(?) then, googling like this post. sorry.. Any advice is helpful, appreciate you all!
 01_TOP.png (421.09 kB. 1953x1304 - viewed 351 times.) 02_GND.png (138.12 kB. 1953x1302 - viewed 379 times.) 03_POW.png (198.43 kB. 2131x1422 - viewed 280 times.) 04_BOT.png (133.41 kB. 1954x1303 - viewed 311 times.)

[nctnico]

The one thing that is true in general, is planes/pours have more capacitance to the ground plane

This effect is actually quite small. Even on a very large board this only adds up to several tens of pf. A significant portion of the capacitance of PCB traces (running over a plane) comes from the fields at the edges, not so much from the trace itself.

An option is to fill all unused copper with a ground poor but it will need via stitching to bridge the gaps.

@kikyw
That board routing is pretty bad!
There should be at least 1 solid ground plane. No slots and no traces in it. Heck I even see signals running over the slots in the groundplane. They should have used the power layer as a routing layer, not the ground layer!

Personally I would have routed this design with traces on top & bottom, a solid plane on the ground layer and copper pours on the power layer. Maybe a few difficult traces on the power layer but a few at most. And sprinkle in a few decoupling caps to tie the power and ground plane together from an AC point of view to allow a path for AC return currents. At high frequencies the return current wants to run along with the trace. If it can't you create a large loop area which can emit noise or receive external pulses that may upset your circuit.

I also see some digital signals going into the analog section. I like to put 220 Ohm series resistors on digital signals going into an analog section to soften the edges.

[tszaboo]

The one thing that is true in general, is planes/pours have more capacitance to the ground plane

This effect is actually quite small. Even on a very large board this only adds up to several tens of pf. A significant portion of the capacitance of PCB traces (running over a plane) comes from the fields at the edges, not so much from the trace itself.

An option is to fill all unused copper with a ground poor but it will need via stitching to bridge the gaps.

@kikyw
That board routing is total crap!
There should be at least 1 solid ground plane. No slits of whatever in it.

That's true it is only a few pF, but the ESR and ESL of that few pF is very very low, so it provides excellent bypassing for RF frequencies. Therefore it is essential for any sort of EMC compliance. And yes, I agree that the routing needs a lot more considerations, than this. But I would agree that even the schematic might need it, IDK why you would introduce digipots for a resistance measurement in the first place.

OP: Copper on the PCB is free, adding copper is not going to make your board worse. If you have a plane, ~90% of it is supposed to be copper.

[nctnico]

The one thing that is true in general, is planes/pours have more capacitance to the ground plane

This effect is actually quite small. Even on a very large board this only adds up to several tens of pf. A significant portion of the capacitance of PCB traces (running over a plane) comes from the fields at the edges, not so much from the trace itself.

An option is to fill all unused copper with a ground poor but it will need via stitching to bridge the gaps.

@kikyw
That board routing is total crap!
There should be at least 1 solid ground plane. No slits of whatever in it.

That's true it is only a few pF, but the ESR and ESL of that few pF is very very low, so it provides excellent bypassing for RF frequencies.

Only at several GHz! A 10pf capacitor has an impedance of 16 Ohm at 1GHz so even for high speed SOC circuits the effect is minimal. A 1uf 0402 sized capacitor is more effective at 1GHz.

[Fgrir]

Only at several GHz! A 10pf capacitor has an impedance of 16 Ohm at 1GHz so even for high speed SOC circuits the effect is minimal. A 1uf 0402 sized capacitor is more effective at 1GHz.

How small are your boards that you think 10pF is a reasonable number for total plane capacitance?  Saturn PCB says you can get that from 250mm^2 plane area even with a 1mm plane spacing.  Most of my multilayer boards have hundreds if not thousands of pF from the plane layers.

[nctnico]

My estimate is that for the 4 layer design from the OP the capacitance ends up in the tens of pf ballpark given the various power planes. Taking current spikes into account it is clear that such low capacitances do not help (much) for decoupling. The 10pf number is just to show that the impedance is quite high. Even at 100pf you are still looking at 1.6 Ohm @1GHz. On a multilayer board (say over 8 layers) you can have the dielectric so thin that the capacitance between the planes is much higher indeed but it still isn't a magic pill.

This video shows that the impedance just from the power planes only starts to have an effect at high frequencies (near 1GHz):


If I'm not mistaken is also shows that the board with decoupling capacitors has a lower impedance overall.

Edit: also keep in mind that power planes can and will resonate; they are not perfect capacitors at all. I have done some interesting experiments in the past to see how usefull capacitive coupling between layers actually is isn't.

[Fgrir]

True, there are a lot of different power rails in there.  There is probably the potential for a few hundred pF available for the whole board but that might end up being less than 100pF per rail.

I just can't believe they added bottom SMT components just for 7 resistors.  Certainly there was space on the top side for those.

[T3sl4co1l]

You mean tens of pF for the power nets shown?  Perhaps.

Full planes are typically low nF!  Small in comparison to the 10s or 100s of uF wired to them, certainly, but also not suffering the ESL of the components.

As for the layout shown, yeah, cardinal sin is crossing traces over slots in the ground plane -- and making slots at all.  (The 'L' slot on the left may be fine, though there's one wild trace going over bare board which should be adjusted, and a, digital bus I think, crossing right over it.)

And as for whether that is a problem -- who knows, maybe the digital levels aren't switching often enough, or fast enough, for the size of those cutouts to be a problem (as with the frequency response (dynamics) of mechanical structures: cutoff frequency is inversely proportional to length).  The bandwidth doesn't look to be particularly high, and some filtering might be sufficient to account for digital noise.  Then again, that 24-bit ADC there will be quite sensitive, and as a guess, the layout around it is probably nowhere near good enough to get the expected ENOB and bandwidth it's capable of.

Tim

[nigelwright7557]

For something like a power amplifier I would use thick traces for output power circuit.
I would use copper pour to ground around input circuit.
I would then star ground all the circuit.

I remember my first pcb, a USB audio mixer.
I built it up and got 1VAC of noise on output !
50HZ was getting in everywhere.
The problem was  I just laid tracks any old how, even mixing in power supply and audio grounds.
The 50Hz was getting in the audio ground and was being amplified up to 1VAC.
So reworked the pcb keeping power supply separate and only connecting grounds at one point on pcb power connector.
Was totally different with almost zero hum.

I now use same principle even for digital stuff.

[tszaboo]

The one thing that is true in general, is planes/pours have more capacitance to the ground plane

This effect is actually quite small. Even on a very large board this only adds up to several tens of pf. A significant portion of the capacitance of PCB traces (running over a plane) comes from the fields at the edges, not so much from the trace itself.

An option is to fill all unused copper with a ground poor but it will need via stitching to bridge the gaps.

@kikyw
That board routing is total crap!
There should be at least 1 solid ground plane. No slits of whatever in it.

That's true it is only a few pF, but the ESR and ESL of that few pF is very very low, so it provides excellent bypassing for RF frequencies.

Only at several GHz! A 10pf capacitor has an impedance of 16 Ohm at 1GHz so even for high speed SOC circuits the effect is minimal. A 1uf 0402 sized capacitor is more effective at 1GHz.

The ceramic cap is actually going to be quite ineffective at 1Ghz. Took a quick look at a specific component, 885012105006, had 1 Ohm impedance at 1 GHz. A stackup that I usually use has 0.711mm core, 100x100mm board would place it at 573pF with standard FR4. For a quick reactance calculation, this is 0.25 Ohm, which is better than the 1uF cap. And it is everywhere. And free.

[nctnico]

But the trouble is that that capacitance isn't present at a single point. Just measure it with a VNA or spectrum analyser with tracking generator like shown in the video I linked to. The answer for this effect probably lies in the electric field propagation delay. At some point a power plane becomes a resonator.

[T3sl4co1l]

TDR is also something doable.  As I recall, planes tend to look like ideal capacitors, with a tiny discontinuity basically due to TL-connector-board stubs (and by TDR, I mean like 20ps risetime, so this includes features like pads and vias!), and then an ideal capacitor after that.

Analytically, we can expect a via into a plane looks like an inductance of mu_0 h ln(R/r), where R is the radius to anything of interest (e.g. nearby via fence), r is the radius of the via in question, and h is the plane separation height.  This is a few nH for practical values, so adds with the via, trace and component body inductances as we would expect.

The full-field version of this considers the via as a boundary condition, and waves propagate radially from it; eventually reaching other boundary conditions and reflecting or scattering off them (other vias, plane edge..).  We can see intuitively that, as the wavefront propagates, its circumference grows proportional to time, so the impedance is reciprocal with time (which is to say, an inductive characteristic).

The impedance of this propagation mode is quite low, so even if it has poorly damped reflections, their effect won't be severe on the circuit.  (The Q is also fairly low, say in the 10s, due to the losses of FR4.)  Which we kind of see in the video: the peak at -40dB is still a mere 250mΩ.  Not exactly stellar for a beefy FPGA or CPU, but more than enough for most MCUs and various RF application.

Interesting by the way, that the measurement changes significantly with capacitors installed, even at high frequencies.  Probably, the fact that anything's connected to the via stubs, is what we can blame for this effect; that is, with them completely disconnected, waves are able to propagate relatively freely.  It's not that the capacitors are irrelevant at high frequencies -- just that they aren't dominant.  And, probably something like, those stubs will have modest AC resistance at such frequencies, so, even though those stubs are inductive up there, it's yet another source of losses.

Tim

[free_electron]

nothing on this board (looking at the silkscreen) requires impedance control. Routing is old-school one layer horizontal, another layer vertical... they didn't bother trying to do a real layout job.

i would use one ground layer , one power layer and flood islands.

[nctnico]

nothing on this board (looking at the silkscreen) requires impedance control.

Yes and no. A poorly routed trace can pickup HF interference which can cause excessive noise in parts of the circuit. Not really impedance control but still HF routing rules to adhere to. Even if the circuit itself is low frequency (although the microcontroller likely runs at tens of MHz and could produce nasty, high speed edges), you can still get high frequency interference. Given that the mounting holes are isolated I assume the board goes into an unshielded plastic case???

[ANTALIFE]

OP, as others have said board layout is not ideal. But I suspect it will work for what you are doing (research?), though some of your resistance measurements may be more noisy than expected

If however this board is to become a commercial product (as in go through EMC testing) then the tracks and stackup will need to be revised. Up to you how far down the rabbit hole you want to go, but if you are curious then I suggest starting with this video (11:20 to 14:50 will give you a good idea on what everyone means when talking about current return path)

[KE5FX]

It doesn't matter what the capacitance of a power plane is.  The RF current you are trying to isolate and confine is not going to spread out all over the plane... and if it did, you would want to do whatever it took to keep that from happening.  It will follow the path of least inductance.  A capacitor made from two 100 cm^2 plates isn't going to act like a capacitor made from two 100 cm^2 plates in any scenario where you think you might benefit from such a capacitor. 

Since you don't have infinite layers to work with, you have to decide what's better for your design, a large power plane or another routing layer.  I don't do high-power RF work, so I've never seen a situation where that decision favors the power-plane approach.    There's a case for using good-sized chunks of copper to deliver power to FPGAs and CPUs and the like, but they shouldn't be thought of as if they were ground planes or laid out like them IMO.