Power plane - via connect style

[c64]

I want some vias to connect directly and some with thermal relief. Most of the vias are direct connect, but some are inside or touching pads - I want them to relief connect.

Is there an easy way to do it?

[Wilksey]

You can have a look at the design rules under the polygon connect and set thermal relief to the rule.
Design->Rules->Plane->Polygon Connect Style->Polygon Connect (default style on mine).
You can change default rules or add a new rule for a specific plane, net names etc.

[c64]

How? Obviously, they are all on the same net.

I can make the vias I want to relief to have different diameter for example, but still don't know how to write a query for Design Rules.

[T3sl4co1l]

You mean the via is in a pad on one layer, and in a plane on another layer?

Can't do rules between layers, except for the few rules that are hard-wired to do so (e.g. soldermask to trace, silk to solder).  This is not one of them.

Better to avoid via in pad, because of solder thieving as well as heatsinking.

Tim

[c64]

Plane is internal power plane. Via doesn't need to be in the pad, can be touching it.

See the picture. All vias go to internal planes. I want resistor to be connected directly to the internal plane, and capacitor to have relief.

[PlainName]

Wild guess: use a specific via template for the in-pad vias and add the template name to a pad class. Then define a rule for that pad class in the polygon class you're pouring.

[Guy Shemesh]

Hi c64,

I'm referring to your image with R1 and C1. I would not recommend doing this, if fact I think it is a bad practice.
I do understand the reasoning though, placing the vias as close to the pads (and on the sides) reduces the inductance and hence increases the effective decoupling frequency range.

But, placing the via partially on the pad has several disadvantages, the first was already mentioned, the solder paste might flow down the barrel. you could plug or tent the via and it does help but better would be to avoid this issue altogether. Further, much more important issue is the much increased thermal variability between the SMD pads on your design.
Think of your assembly factory, on which profile temperture they are supposed to work if they have smd pads that are very cold (C1) while others heat up quickly (R1)? there is the possibility for this circuit to have cold welds that may look soldered to the eye but in fact are very fragile. Again, nothing that can't be solved but should avoid.

What I would recommend you to do (if you need super decoupling powers  ) is having 4 vias for C1, 2 vias for each pad resting on the sides. do leave some minimal neckdown of 1mil and don't let the annular ring touch the pads. I always recommend the vias to be "direct connections", without reliefs.

By the way, I have written some 10 commandments for proper PCB design... these are really important practices I encourage you to understand.  skim to somewhere in the middle of the page to see it and feel free to ask questions.

With all that said, again referring to your picture of C1, I think adding 1mils of a neckdown (i.e a trace) and tenting the via and you'll be fine as is.

Guy

[ahbushnell]

You mean the via is in a pad on one layer, and in a plane on another layer?

Can't do rules between layers, except for the few rules that are hard-wired to do so (e.g. soldermask to trace, silk to solder).  This is not one of them.

Better to avoid via in pad, because of solder thieving as well as heatsinking.

Tim

Some devices require vias in the E-pads to heat sink the device.