Electronics > Altium Designer

How to disable or avoid "Un-Routed Net constraint" checking for some pins

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msimunic:
Hi all,

I have a connector onto which another device should be plugged and that device will give few different power rails. Same rails (same net labels) are present on pins on both sides of connector.
Some of those rails I don't need in my design, thus I'm don't want to make connections, but I do want to have net labels in schematics (for a documentation).

In PCB layout, because of multiple pins with same net label are not connected, DRC is giving "Un-Routed Net constraint" error for all of these pins.

Is there a way to avoid check for Un-Routed Net constraint on some pins/nets? - Just to have clear and error-free DRC report.

Small digression:
Yes, I can remove net labels and place text labels for documentation. I would prefer to have net labels.
Creating a blanket and putting those nets in a Net Class, then changing DRC Rules for that Net Class didn't help to stop DRC check.
Maybe I've made a mistake about Rule conditions, but I didn't find it.

I guess, everyone run into this kind of question sometimes.
It looks to me like a good candidate subject for Zachariah Peters on Altium Academy.

asmi:
I typically deal with that by creating a custom symbol for that connector, which would include net names as pin names. This symbol would reuse the same footprint as the "generic" symbol for that connector, so pin designators are the same, but pin names are different. For example, I've attached a version of a 10 pin tag-connect symbol which is specialized as a Xilinx programming connector.

thm_w:
You could unlock primitives -> edit jumper IDs for those pins you know are joined -> lock primitives

https://www.altium.com/documentation/altium-designer/pads-vias#!jumper-connections

c64:
I remember I had similar issue. Trick with jumper IDs didn't work for some reason.

I ended up adding dummy copper layer with dummy traces connecting required pins. When hide this layer and exclude it from gerbers

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