Is important to use an unique via when connecting planes?

[JeyNerNer]

Hey all,

I'm working on a PCB in Altium with 4 layers. The second layer is for VCC, while the third one is for GND, and I have made a VCC plane and GND plane in each layer. The thing is that I want to connect the VCC and GND pins in the layer one to the layers two and three (respectively), using vias. I remember on the college a teacher once told me that I should use an unique via for connecting each pin, but now I'm not sure about that and my coworkers say I'm wrong. Is it important to use an unique via or it has no sense? I think it was related with EMC or something like that, but I'm not sure.

I'm aporting an image clarifying what I'm saying. As you can see in the picture, I used 3 vias instead of only 1.

[free_electron]

it depends. in general you do not want currents, especially pulsing currents, to share a via. vias have impedance and shared currents lead to offsets and intermodulation ...

[JeyNerNer]

Thank you so much for your answer. This is a project for programming a motor driver of a stepper motor. I guess I will keep the individual vias.

Thanks!

[T3sl4co1l]

Simple.  All you need is this complicated procedure!...

For each configuration, consider the impedance from each pin to ground, and between the pins.  If this impedance or gain is expected to impair performance, eliminate that configuration.

Impedance is defined as the ratio between voltage and current.  So, if a device draws say 100mA pulses and should have less than 0.1V of ground bounce, it should have an impedance under 1 ohm.  Simple enough.  Of course, this is in terms of AC, so we need to say that's 100mA and 0.1V at some frequency (AC steady state analysis), or that we're considering some combination of dV/dt and dI/dt (transient analysis).

For example, say your motor driver switches 100mA in 100ns, or a current slew rate of 1A/us.  The traces and vias pictured are probably on the order of 10nH.  V = L dI/dt or about 10mV peak.  Not much.

If that current flows through a current sense resistor, for example, which reads on the order of 100mV, I might be concerned, and would suggest tighter layout (shorter and wider traces, or pours; perhaps multiple vias flanking the pads), and also Kelvin connections and perhaps adding RC filters (to reduce the peak sense voltage).

The same analysis applies to +V rails, by the way, with the impedance being raised by (series) inductances and resistances, and lowered by (parallel) capacitances.  The power supply network as a whole should be considered, as a filter network, and impedance or gain (transmission) peaks should be considered carefully (and damped where offensive).

All of which can be hand-waved to a certain extent, or constructed in and analyzed by, say, SPICE (the construction being an approximation of the real circuit, because a real circuit contains distributed elements like traces and planes).

Tim

[thm_w]

In your case it likely won't matter, but Vias are essentially free so better to have them there.
*there is a slight cost of layer space.

BTW its not required, but you can put the via even a bit closer to those components.