0.65mm BGA rules

[ali_asadzadeh]

Hi,
I have done more than 20 designs using 1mm pitch BGA, mainly Xilinx FPGA, But now it seems that everything that's good, like the New Cortex Devices are offered in 0.65mm and 0.5mm BGA.

I want to know what are the design rules for cheep manufacturing of them, JLCPCB seems can not meet the requirements for 0.65mm BGA, or Am I missing something!

What sort of Track size, Via size etc... do you use? what are the cheapest PCB manufacturers that can do the job, I think most designs can be done on 4-8 layers,

I'm interested in The i.MXRT and i.MX8 parts from NXP, and have designed a 4 layer PCB for i.mXRT but, JLCPCB seems they can not produce them, because of the Via and track spacing! any Ideas on general rules and cheep options are highly appropriated.

Note: the i.MXRT part is a 196BGA full grid array with no free space in the center of the cheap, so AN10778 from NXP does not apply there!

[Pseudobyte]

Taken from AN4982 from NXP.


JLC can do 3.5mil copper to copper. They have a spec for via to trace at 5 mil, and the minimum via you can use is 0.2mmx0.45mm.



unfortunately using those specs you can't do it with the standard bga pad. If you reduce the pad to 8 mil round it appears to just barely fit, albeit at the cost of the solder joint.

[ali_asadzadeh]

Thanks for the feedback.
See this changes! still not doable, JLC needs a 5mil clearance from via to track which can not be done! Any Ideas?

[Berni]

Thanks for the feedback.
See this changes! still not doable, JLC needs a 5mil clearance from via to track which can not be done! Any Ideas?

Go to a better PCB manufacturer and pay them an absurd amount of money to make yours prototype boards. It only tends to come down to a resonable price once you ask for the boards in large volumes(Even at people geared for small runs like JLC or PCBWay). The combination of lots of layers, ENIG finish, fine track with and small hole size makes the price really go up when ordering only 5 boards. If you can get away by not having vias in between pads then it tends to be more reasonable, but not all BGA packages are designed to let you do that.

And if you do find a manufacturer that won't change over 400 bucks for prototype boards do share there name.

[xlnx]

ali_asadzadeh - I'm wondering the exact same thing. If you find a solution I would be very interested!

Also - what is your experience with 0.8mm and 1.0mm pitch on the JLCPCB process - are you able to run 2 tracks between BGA pads? What is your strategy to make 4-6 layer boards with Xilinx BGA packages?

Thanks for bringing this up!

[ali_asadzadeh]

ali_asadzadeh - I'm wondering the exact same thing. If you find a solution I would be very interested!

Also - what is your experience with 0.8mm and 1.0mm pitch on the JLCPCB process - are you able to run 2 tracks between BGA pads? What is your strategy to make 4-6 layer boards with Xilinx BGA packages?

Thanks for bringing this up!

.
Thanks, I have not done 2 signals between the balls, but 1 signal is very easy, and 1mm and 0.8mm is the same, it's very easy and normal to do it