Buses in Multichannel Designs

[sacherjj]

I am making an individual power point controller that has a MOSFET switched jack.  These are controlled by an 8-bit 12V shift register.  Then I'm chaining 3 of these together per board.  So I will have 24 power jacks that are individually addressable.  These are chained to two additional boards (shielded ribbon for 18" or so) for 72 points per shift chain.

I plan on driving the data and shift slowly to enhance reliability.  The bandwidth of powering on and off is VERY low and I will be driving through MOSFETs to get from the MCU voltage up to 12V that all of these boards operate on.

I have this structured as a 3 level hierarchy in Altium.

Single Channel:


Shift Register Level with 8x Single Channels:


Top level with 3 shift registers and linking Qs into next levels Data In:


I get errors for Bus Slice TP[1..8].  This is defined in the mid level, but it looks like I can't have it automatically generate buses in the mid levels for each bank.  Although it looks like this is exactly what is done in the example here: http://techdocs.altium.com/display/ADOH/Creating+a+Multi-channel+Design

I was unsure about QD1 <-> SD2 type linking, but it seems OK with that.  Is there a better way of doing that?  It sort of messes up my net names.

[T3sl4co1l]

Do you have automatically generated net names configured properly, under Project Options?  You'll want something like, "append channel index to name", or you can write your own identifier string.

I see the component designators already have this, so check that the net names do, too.

The "net linking" I don't think should work, but maybe that's how you're supposed to do it?  I've needed to do that before, but didn't try; multiple net names on a single wire is so thoroughly against the design philosophy of Altium.... but I wouldn't put it past them to have it be done that way.

Tim