Duplicate net names on top sheet when using bus between child sheets

[smoothVTer]

I've used my google-fu and scoured this forum to no avail, so I shall ask your wisdom, ladies and gentlemen:

Here's my top sheet:


Here's the child sheet in question, MCU.SchDoc:


The child sheet has a bus  AXIL[3..0]    I run this bus to an output port, also named AXIL[3..0], for use in another sheet later on.       I created sheet symbols from the constituent sheets below and placed them in the top sheet.   Then, I want to run the AXIL[3..0] bus from the symbol of the MCU sheet to a header on the top sheet.  I want the bus to 'open up' near the header, split into individual signals again so I can route AXIL0,1,2,3 to whatever pins on the header I want.

However:   when I try to name the individual signal wires from the bus on the top sheet, I get compilation errors about "Duplicate net names Element[0],[1],[2],[3]":


At first I thought this is because I have the global settings for flat/hierarchical design incorrect.  So I read over the documentation 3x and thought I had all my ducks in a row:




 

All options for net scope seemed okay and what I expected, so now I am stuck for quite some time.

How do I break out individual signals from the AXIL[3..0] bus on the top sheet?   If I can't name the wires the same name on the top sheet as in the child sheet, how does one establish proper connectivity going from child sheet -> top sheet -> I/O connectors?

[radar_macgyver]

Use a harness?

[D3f1ant]

The joy of hierarchical designs 

On the top sheet you havn't labeled the bus AXIL[3..0]. In this instance, I would change  the net identifier scope to Global,  I think then it will connect up on the PCB and not give you any compile errors.

Hope that helps 

[T3sl4co1l]

AFAIK, the bus object doesn't actually do anything.  It's only used to indicate, graphically, where net labels come from.

The one exception is fanning out buses from REPEAT sheets, but that's distinctive: a wire is used to name the bus, then the nets are enumerated.

At least, that's what I recall, and that's how I've used them.  Harness is what you're looking for, here.

Tim

[D3f1ant]

Yes exactly, it does end up a graphical representation but with some error checking.  In the OP example, if you don't label the bus, you will get compile errors, but it may have actually generated a valid net list for the pcb anyway.
The errors can make a useful sanity check, I think its preferable to not suppress but fix the cause. Harness might work as well, I haven't used that feature much.

Sent from my SM-N930F using Tapatalk

[smoothVTer]

Thank you everybody!     Wish I could buy ya'll a beer, or a soda, whichever you prefer.

The problem was indeed the missing label on the top-level output bus.   As soon as I put another net label on the TOP sheet bus AXIL[3..0], I could name the wires breaking out from the bus to the header what I wished:  AXIL0, AXIL3, AXIL2, AXIL1    It did not matter whether my Net Identifier Scope was set to Automatic / Hierarchical in this case.