Exposed Pad Ground Termination??

[skeematics21]

How do i connect the Exposed 20-VFQFN  pad of U1-21 to ground? 

[DerekG]

How do i connect the Exposed 20-VFQFN  pad of U1-21 to ground? 

Just place a track from the GND net on the lower RHS corner of the flat pack to the central earth plane (pin 21).

I believe the auto-router did not complete it due to either:

1/ a keepout area that is set up within the quad pack (so modify the keepout area to allow you to manually route to the pad) or
2/ the design rules for the auto-router are set such that there is not enough clearance to allow a track though (so adjust your design rule clearances to allow you to get a track through - or else you will get a DRC error when running an integrity check of the board).

Also, just a pointer of good advice - see the VDD track (SMD layer) immediately under the symbol U1 that forms a "V". This can allow the etchant to pool against the V which can eat through it. Just change the "V" for a "T" intersection & all will be good.

[T3sl4co1l]

Eww, so ugly!

You have a ground plane under that thing, right?  If it's a two layer board, fill both sides and stitch (move routes as needed to save vias and improve design); if four layer, VCC and GND shouldn't even appear on the surfaces except to connect to vias.

Tim

[Bud]

If you refer to inability to stich the pad to Gnd because of the DRC error, I remember what I did was I opened the PCB library that contained that footprint, removed the 4 small vias from the exposed pad and resaved. Refreshed the footprint from the library and stitched the pad to Gnd using my own vias. Do not know if this was the best way to fix it but resolved the issue quickly.

[skeematics21]

Thanks all.. Now how do i do a polygon pour "solid fill" just for the holes in the thermal pad?

[T3sl4co1l]

Not sure if this would work, but...

Create PolygonConnect rule:
IsVia AND (Owner='refdes')
Direct Connect

And maybe more conditions, say if you want to select just one polygon, you could name it and add that to the conditional too.

Via-in-pad shouldn't have any voids at all.  If this is where the via connects to another layer, you might as well just set direct connect on all vias (IsVia) (they're vias, not soldered pins, they don't need thermals anyway!).

Tim