Hi,
I have a design with blind vias (top to mid layer 1). Layer pairs are set up in the layer stack manager, and the design and created Gerbers look right and look to agree with each other. However, when using the 'fabrication Outputs' > 'Test Point Report' to create the IPC-D-356A export, the .ipc file generated has a continuation hole through the rest of the design, which caused errors when relinked to the Gerber files by our PCB supplier.
I have tried a new, smaller, noddy design and this creates the same issues. An exert of the IPC file is:
317DGND VIA - D0200PA00X 000600Y 004350X0000 S3
307DGND VIA - D0200PA01X 000600Y 003800 S3L01L02
027 VIA - A01X 000600Y 003800X0000
317DGND VIA - D0200PA00X 000600Y 005450X0000 S3
317DGND VIA - D0200PA00X 000600Y 004900X0000 S3
307DGND VIA - D0200PA01X 000600Y 001600 S3L01L02
027 VIA - A01X 000600Y 001600X0000
307DGND VIA - D0200PA01X 000600Y 001050 S3L01L02
027 VIA - A01X 000600Y 001050X0000
307DGND VIA - D0200PA01X 000600Y 003250 S3L01L02
027 VIA - A01X 000600Y 003250X0000
307DGND VIA - D0200PA01X 000600Y 002150 S3L01L02
027 VIA - A01X 000600Y 002150X0000
307DGND VIA - D0200PA01X 000600Y 002700 S3L01L02
027 VIA - A01X 000600Y 002700X0000
317DGND VIA - D0200PA00X 005900Y 000500X0000 S3
So the S3 (full stack) vias are noted correctly, but the S3L01L02 vias are followed by the '027' continuation hole. As I say, these holes do not appear in the design and the Gerber files look correct. Is there a setup issue which is creating this anomaly?
Regards,
Pete
Is this