EEVblog Electronics Community Forum
Electronics => PCB/EDA/CAD => Altium Designer => Topic started by: Tsiligiris on April 23, 2018, 05:30:42 am
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Hello everyone,
there are times that track is not on the center of Via and we need to final check all the Vias on all layers. On the attached pic, the DRC is not giving me error and it's normal since +3.3V is connected (even not correctly) to the Via.
Is there a way (like a Rule?or something) to detect this?
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Well, I guess DRC checked your minimum copper width rule for that net and it passed, so technically there is no problem but I agree it doesn't look right.
I have never used this script but it might help you:
https://github.com/Altium-Designer-addons/scripts-libraries/tree/master/IsPadCenterConnected (https://github.com/Altium-Designer-addons/scripts-libraries/tree/master/IsPadCenterConnected)
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Cannot Run the script on Altium09 or Altium18. Displays various errors like the attached picture.
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The attached script has some minor API call changes from the above script which enable it to run on AD15 (quick test OK but YMMV).
It highlights pads which do not have a track connected at their centre.
Unfortunately it can't be easily modified for vias because IPCB_VIA does not have the method BoundingRectangleOnLayer()
So, I have been no help at all. :-\
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Anyway thank you :)
Let's hope someone has a solution to share
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never used altium, but seeing as its passing with the neck down due to being wider than the minimum, why not reduce your minimum to the trace width, and investigate what comes up?
Or if there is a way to bulk change via size, why not save a copy, change all vias to a size smaller than there connection radius, then re-run DRC to see what now has a gap.
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In Altium 18 there is a rule that you can check, see pic, also I remember an old design secret that might help you: https://altiumvideos.live.altium.com/#Detail/1225 (https://altiumvideos.live.altium.com/#Detail/1225)
BR
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That's a nice feature, maybe new in AD18 and is the best answer since OP has AD18.
Its not in AD15.
https://www.altium.com/documentation/18.0/display/ADES/PCB_Dlg-BrokenNetRule_Frame((Un-Routed+Net))_AD (https://www.altium.com/documentation/18.0/display/ADES/PCB_Dlg-BrokenNetRule_Frame((Un-Routed+Net))_AD)
Check for incomplete connections - with this option enabled, the following additional checks on connectivity between applicable design objects are made:
Track/Arc to Track/Arc - checking that the centerlines, or centers of the ends of the connecting track/arc segments, coincide.
Track/Arc to Via - checking that the centerline, or center of the end of a track/arc segment, is placed on the center of the via.
Track/Arc to Pad - checking that the centerline, or center of the end of the track/arc segment, is placed on the shape of the pad.
Via to Pad - checking that the center of the via is placed on the shape of the pad.
Via to Via - checking that the centers of the two vias coincide.
Polygon to Track/Arc - checking that the center of the end of a track/arc segment is overlapped by the polygon.
Polygon to Pad/Via - checking that the center of the Pad/Via is overlapped by the polygon.