Power plane clearance - on all layers

[penfold]

Hi,

I was wondering if anybody has a solution to apply some constraint that would ensure that there is no power plane lies under a particular trace, on any layer.    A more automatic method to ensue that there is minimum capacitance to ground for a particular trace.
I know there are manual ways of doing it, just wondering if there is some way that would either do it automatically or flag up a design rule check error