Import Altium projects to Xilinx ISE

[xenex92]

hello. first of all, I am new here, and I am sorry if I opened the thread in the wrong place. if an admin will note me, I will move it in the indicated place.
second of all, I am a student, new in the Altium field, and I am trying to program my FPGA board (Spartan 3E - 250 from Digilent). as many of you do know, being a student isn't so profitable, so I am trying to import my schematic from Altium without a JTAG cable. an older student made it without that cable. he imported the projects into Xilinx ISE and programed the board, like programing with one of the DEMO's given from Xilinx website.

do any of you know how did he do it? he would't tell me, but there must be someone who knows. buying a JTAG cable is not one of my priorities right now, and I realy need to start working on that board.
thank you.

[xenex92]

Never used AD to do FPGA, and frankly, I don't believe there are people really use AD to design FPGA.

Anyway, you may copy all hdl files to ISE, and create a new project from ground up.

It will be harder if you used schematics hdl entry, though.

I agree with you. AD is a powerfull tool, but very complicated. Unfortunedly, using AD is one of my teacher's requests.. I will try that method and come back with feedback.

[Someone]

AD provides the front end and hands off HDL to the FPGA vendor tools, then the vendor tools run through and provide their normal outputs. The HDL wont be very readable but if you're just wanting to use a different programming cable the final routed design will be there so you can create any output you like from the ISE tool.

[David Spicer]

Hi

Since you'll have to use the  Xilinx place and route tool, you should be able to create a bitstream that you can download using a xIilinx download cable. Alternatively, you _should_ be able to use the EDA netlist to feed to Xilinx ISE. As I recall, Altiumn wrote  their own synthesiser. That must give you an output file compatible with the Xilinx P &  R tool. I can't remember what the extension is, I think it is .NGD (netlist generic database) but it will be easy to find out from the docs. I

I confess I'm not entirely sure of what you are asking. Does the Digilent board put the bitstream into a prom of some kind.If so, the Impact tool will create various file formats for a device programmer.  I  cannot see how you can download your bitstream without some form of jtag cable, unless you can remove the bitstream prom and use a device programmer.

If you could elaborate a bit I can be more helpful. Meanwhile,the intermediate files that are produced to change tools (sch->HDL, HDL-> synthesiser, synthesizer-> P&R, P&R to bitstream, _should be in EDIF formats and exchangeable between tools. There are, for example, numerous third party synthesisers from (e,g.) Synopsis, Aldec and many more. They all produce a generic EDIF file as only the manufacturers can do the Place and Route stage.

One more thing, Xilinx are pretty helpful to students, you can get Webpacks for all ISE versions for nothing. The AltiumFPGA tools were never much use. I think they were hopelessly over ambitious trying to make a universal FPGA development system. Besides, Using schematic as input is not my preffered choice. It's cheating, and if you look at the HDL output it can be a huge unreadable mess.Learn VHDL or Verilog. You'll be doing that when you get a job!

Frankly I don't see how you can do this without a jtag cable of come sort.