Yes, this diagram. Match up blocks. You already have part of the "power stage" in the TL494. You have the comparator and a ramp generator. You have a direct connection from a pair of op-amps to the comparator: this is your current error amp. The other one cannot be used (unless maybe as a U/OVLO, or some other process variable, temp limit, etc.) so probably just gets strapped off. Voltage error amp has to be a separate chip, and can be as simple as a BJT if you don't need much for regulation, but preferably is an op-amp proper.
TL494 doesn't have a current sense amp so you need to add one externally; the diff amp in the diagram can be a current sense/shunt amplifier, Hall effect sensor, pair of current transformers in the power stage, etc.
All the EAC is doing is comparing inductor current to the setpoint, and that setpoint comes from the EAV. Imagine you were controlling, by hand, a current source to regulate output voltage: you'd be adjusting this setpoint manually (pot from VREF to GND, say). But you're looking at VOUT in relation to VSET and adjusting it accordingly, which an EA can do automatically, and much faster than human reaction time.
And we can limit the EAV's output range, so it only ever commands a current setting that is within nominal design range.
We physically cannot overcurrent the power stage this way, not under normal operation at least.
Put another way: section off the power stage, PWM, EAC and sense amp. Wrap all of that into a block. What does it do? It takes in some power (how much, doesn't matter, other than for a buck, Vin > Vout), sends out a current, and that current is in proportional to the input voltage (current setpoint / EAV output). We have a transconductance amplifier.
Which also means we can connect
unlimited power stages in parallel if they are of this type: where the inductor current is controlled locally, in loop with its respective EAC. Such a circuit is highly scalable.
Finally, for dynamics, notice the gm amp (the whole power stage + EAC block) has a dominant-pole response cutting at a well-defined frequency, given by inverter gain, inductance, and EA compensation. We put this inside the voltage loop, which has a dominant-pole response cutting at a somewhat lower frequency, given by gm amp response, the capacitor, and EA compensation.
This pole can be higher than 1/sqrt(LC), thus we have better performance (lower output impedance, and to higher frequencies) than a voltage-mode control which has to have the compensation pole below the LC resonance.
Overshoot is not at all assured: the EA can approach steady-state gradually and settle in, or too quickly and overshoot. There is no RHP zero as in a peak current mode control (although I don't actually know the details, and probably analysis is a bit worse in DCM; ACMC somewhat assumes CCM, or more to the point, is easiest to understand in CCM), so a simple 2nd or 3rd order overall response, of whatever desired prototype (i.e. Butterworth, etc.), is possible.
PCMC tends to have overshoot, or a compromise in response (slower than might otherwise be expected), due to the RHP zero at Fsw/2, making it a non-minimum-phase system; the control pole is thus forced to be at least a bit lower than this (maybe Fsw/5 or something?). But this is fine, as using electrolytic capacitors for output filtering, they generally need to be more than large enough to meet this, and thus the voltage loop compensation pole is low enough to avoid the zero. A zero can also be added to the compensation (pole-zero or type 2 compensator) to win back further phase margin.
Which, speaking of PCMC, almost every diagram you see of UC3842 has an R||C in the feedback network, which is... just bizarre. It's intentionally throwing away DC gain (and thus regulation and PSRR) just to make it a tiny bit easier to compensate (the limited gain at any frequency, means somewhat less chance for oscillation). Maybe not bizarre, being the best word for it, but definitely lazy. Lazy by both author and reader: another one of those oft-repeated errors that's just good enough to pass, and no one stops to question it. Well, I do, and I disagree.
(The resolution is trivial: put the R+C in series instead of parallel, and adjust values until compensation is optimal.) (There is a further quirk of this, were the R||C sometimes is shown after an optoisolator, when compensation has already been realized on the secondary side around a TL431 or whatever. Which is just silly; the COMP pin can be [over]driven by opto directly, or the error amp strapped as inverting-gain-of-1 with a pair of resistors, no compensation needed or desired. I think I've seen this a few times in TL494-related schematics too, additional compensation after the error amp proper. Go figure.)
Tim
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