CurrentSense Comparators for electronic load

[Jwillis]

I managed to get 4 Mosfets working equally through varying Currents and Voltages  by using one current sense of a Master reference Comparing the current sensors of each remaining Mosfet to drive those the remaining  Mosfet drivers in parallel . But calibrating them was complicated. I was wondering if I could reference of each current sense in series to make calibration easier. I don't have an accurate  circuit diagram with all the information available at this time So I drew up this simplified block diagram to explain what I want to try. Would this work to make calibrating each block easier? 

[Dave]

Compare every slave branch to a single master reference, otherwise your errors are just going to accumulate.

[Vovk_Z]

I don't understand why comparators?
May be something like that (here is usual way to make el. load, X4 is for 1k potentiometer):

[Jwillis]

Compare every slave branch to a single master reference, otherwise your errors are just going to accumulate.

Thanks Dave. the way you describe is the way I have it right now. I see your point now how errors will occur and compound across the series .

I don't understand why comparators?
May be something like that (here is usual way to make el. load):

Your right that that is is the common way of paralleling but the problem still arises that one will load hog more than the others . This is do to each Mosfets having  a different V_gs .Even when selecting  Mosfets to have a V_gs  as close as possible ,the problem of load hogging still occurs.This seems to be much worse when running Mosfets in linear mode as opposed to pulsing .
The idea of the comparators is to make  the currents passed be each Mosfet  equal by automatically adjusting the gain of each driver. So far the concept works but calibration of the gain on the drivers becomes a nightmare . Its easy to calibrate the gain of 2 .But with 4 it gets more complicated. Adjusting the gain of one will change the gain of all others.
Once all banks are balanced the comparators are able to keep them balanced as the voltage the current demands increase.

I have tried to use a simulator but I just can't get the program to work even on simple circuits. Still trying.

[hli]

Your right that that is is the common way of paralleling but the problem still arises that one will load hog more than the others . This is do to each Mosfets having  a different V_gs .Even when selecting  Mosfets to have a V_gs  as close as possible ,the problem of load hogging still occurs

No. In Vovk_Z's schematic, each MOSFET has its own shunt resistor, own feedback loop. This means each MOSFET draws current according to the shunt resistor, no matter what its V_gsth is. You even can use different MOSFETs - as long as they can handle the load you are fine.

[Jwillis]

No. In Vovk_Z's schematic, each MOSFET has its own shunt resistor, own feedback loop. This means each MOSFET draws current according to the shunt resistor, no matter what its V_gsth is. You even can use different MOSFETs - as long as they can handle the load you are fine.

I've done similar circuits with only 2 banks of Mosfets and one always loads harder than the other. They will not balance .Only by adjusting the gain of each driver will they balance but they will not hold that balance at different ranges of current. The temperature difference can be as much a 10^o C between each Mosfet. It's much worse with 4 parallel Mosfets. With the comparators and Active current sense , the circuit I'm building holds each Mosfet within 2^oC of each other and a difference in current of 3 to 4 mA.

[Kleinstein]

The individual control loops should also get pretty good load sharing. The MOSFETs not matter any more. There may be a small difference from the OPs offset, but this should be a small part (e.g. a few percent of the maximum power at most).

With the separate control loops one could also switch off some of the channels and this way get slightly better resolution at low currents.

A point is that the precision depends one multiple shunts and the average of the OPs. With single control loop one can get away with one good OP.  A single high power shunt may also be slightly cheaper than several smaller ones - though not for sure and one still need individual resistors for the current sharing part. Chances are current sharing would be slightly worse as cheaper OPs and resistors can be used.

[Vovk_Z]

I've done similar circuits with only 2 banks of Mosfets and one always loads harder than the other.

- that means some simple mistake in ground wiring. Something like you used too thin common wire or connected it to a little bit wrong point.
If everything done ok then this circuit have very small difference, something like several mA at small currents or less then 5% with large currents.

[Jwillis]

- that means some simple mistake in ground wiring. Something like you used too thin common wire or connected it to a little bit wrong point.
If everything done ok then this circuit have very small difference, something like several mA at small currents or less then 5% with large currents.

I'm sure your circuit is fine for your needs . But why would I settle for 5% when I can have  0.03%at 1 to 10 A. The whole point of the experiment  is to get the best possible balance with what I have for components.

[Vovk_Z]

I don't know why do somebody need to share currents between mosfets with 0.03% accuracy.
And always there is possibility to put potentiometers into every opamp-mosfet module to adjust this.

[RoGeorge]

May be something like that (here is usual way to make el. load, X4 is for 1k potentiometer):

https://www.eevblog.com/forum/beginners/currentsense-comparators-for-electronic-load/?action=dlattach;attach=918004;image

I would like to know how well it performs in practice, what instrument is that schematic from, please?

[Vovk_Z]

It works ok, there isn't only additional resistors 1M÷2M from 1.2V to inv. opamp imputs.
And, C1, C2 better increase to 2.2-3.3 nF.
It isn't from instrument, it is classical usual mosfet electronic load circuit. A circuit is from my last project. I made electronic load for myself long time ago but it was made on universal pcb. That circuit was made for my collegue to he could made modern beautiful (Chinese) PCB for me (I don't like making PCB).

[RoGeorge]

I didn't suspect it of not working OK, just curios of reading the specs because I wanted to build something similar.

[Vovk_Z]

Specs depend on you - you choose mosfet, shunt (and opamp - usual or precision type).
What exact specs do you need to know?
That my module on my last photo with 2xIRFP460 is 250V, 10A, 100W rated. With IRFP460 it works from about 1 V and more.

[Kleinstein]

For stability with difficult inductive sources a CC sink may need a parallel RC at the inputs.  Depending on the circuit something like 0.1-1 µF and 10-100 Ohms in series could be enough.

The other point is that the circuit runs into a kind of windup, when the DUT voltage gets too low (e.g. not connected). So there can be a significant current peak when connecting a source while the load circuit is already turned on. A diode in parallel to R5, R7 can at least shorten/limit the peak a little.

[Vovk_Z]

You are right, here is full schematics with input voltage control:

[T3sl4co1l]

I don't get it, why possible advantage does that system hold, that simply wiring transconductance stages in parallel (see above) does not provide?

I also don't understand the diagram, in that, I suspect you're showing things at a much higher level than they actually are..!?  First off, comparators have no place in a linear circuit -- they are by definition the most nonlinear component.  Changing gain implies at the very least an analog multiplier, which is terrifically over the top for a simple application like this, and again nonsensical in combination with a digital signal (a comparator output).  It might not even be analog, it might be digital instead, in which case it's, I guess, some absolutely complicated mess of a distributed digital architecture, reading mismatch to update gain registers at some rate (every update strobe, perhaps) and... ohh man it's the beginnings of a horror movie!  Or perhaps you've made the error of using the word "comparison" to mean "subtraction", and it's actually a difference amplifier, with well defined gain and bandwidth; but if this is the case, then why not label it as such?  I have so little information to go on, I have to make far too many assumptions in order to begin to make sense of this!

Tim

[Jwillis]

I don't get it, why possible advantage does that system hold, that simply wiring transconductance stages in parallel (see above) does not provide?

I also don't understand the diagram, in that, I suspect you're showing things at a much higher level than they actually are..!?  First off, comparators have no place in a linear circuit -- they are by definition the most nonlinear component.  Changing gain implies at the very least an analog multiplier, which is terrifically over the top for a simple application like this, and again nonsensical in combination with a digital signal (a comparator output).  It might not even be analog, it might be digital instead, in which case it's, I guess, some absolutely complicated mess of a distributed digital architecture, reading mismatch to update gain registers at some rate (every update strobe, perhaps) and... ohh man it's the beginnings of a horror movie!  Or perhaps you've made the error of using the word "comparison" to mean "subtraction", and it's actually a difference amplifier, with well defined gain and bandwidth; but if this is the case, then why not label it as such?  I have so little information to go on, I have to make far too many assumptions in order to begin to make sense of this!

Tim

   

I don't expect anyone to interpret the inner workings of the circuit based solely on a simple block diagram thrown together in a few minutes . The question was whether referencing the blocks in series would work any better over a parallel configuration. That's it.  It was concluded that in a series configuration would probably compound errors.
I didn't include a circuit diagram because its a work in progress and experimental . 

Because no matter how well you pick your components perfect balancing would not be possible since  a tiny difference in threshold voltage between MOSFETs results in a substantial current mismatch . Other factors also effect the balancing like temperature and how well matched the other components are.
The use of differential comparators is is to increase or decrease the gain of each block based on an active current sense. Yes the output of the comparator is digital (either high or low). But I found that I can control the gain of each driver.  By doing this the Mosfets balance much closer together than the conventional way without the need to perfectly match the components I have.
I have a working circuit on my bench doing exactly that. The reason I'm trying to keep the Mosfets balanced as accurately as possible is because of a  limited  amount resources to create an electronic  load to handle very large current loads without  any one mosfet falling out of the  Forward Safe Operating Area (FSOA). Yes I could use more mosfets or different Mosfets  .I could use more heat sinks But I don't have any of that available . So I'm working with what i have.

I have no doubt that that other circuits are adequate for what they are purposed for. And I'm sure that 5% variation is fine for many applications . But I wanted to see if I can try something that might work a little better . And so far it has . All my mosfets are holding within a couple degrees of each other with the currents holding within very small margins of each other. Which is better than how it was originally set up without active current sense and comparators . Better than I originally expected .
It's an experiment . If it works go with it . And I simply don't understand why trying to make something work a little better causes such a controversy.

[T3sl4co1l]

See, that's my point, you're communicating something with the diagram, but what?  It's a language thing -- can you rephrase it, or describe it some other way, or give something more concrete like a preferred implementation (granted that it's "in progress" and all)?  That's all.

As for the description of the problem, "a pairwise balancing mechanism", yes, that is clear -- for a chained architecture, it will accumulate errors.

More generally, say you have N independent current sources, independent in that they're doing their own thing while operating at the same given setpoint.  There are N^2 - N possible (directed) connections between them.  Presumably there would be a way to connect them such that the error between any given pair is no greater than the error of a single correction circuit, and we would probably want to find connections which minimize the number of correction circuits for a given error.

So, if we draw the graph, plotting a node for each current source, and an edge between any two that are correcting in this way (and note that it's a directed graph when our correction circuit only works one way, from a reference to a destination), we can see that the chain architecture has the greatest maximum distance between any two nodes on the graph -- it's actually the worst possible!

If we rearrange instead for a star topology, we can use one node as the reference for the other N-1 nodes, and incur only one correction error at most.  We still need N-1 correctors, and there isn't any obvious way to do better without leaving any nodes completely untouched.  This falls short of a rigorous proof, but I'm comfortable with it.

Here's the trick though: say we declare that reference node is an abstract signal, not actually a current source; we add another current source to maintain the same total current, so now we have N correctors for N current sources with 1 reference.  We can suck each corrector inside its respective current source, say integrating it into the driver circuitry.  There may be some savings in component count / cost this way.

This now describes just any regular old opamp-per-FET architecture, wired up as needed to maintain accuracy.  Mind, there might be two wires for setpoint and setpoint ref, to avoid ground loop errors where connections between shunt resistors can introduce errors.  We might end up needing two or three opamps per stage to resolve the differential voltages (ref, shunt and gate drive), but that's fine.

We can use the same components in each unit, achieving arbitrary accuracy -- 1% is trivial and probably doesn't even need differential sense, 0.1% you need costly resistors and probably differential sense, 0.01% or better and you'll probably need to calibrate each section individually, perhaps even temperature correction as well.

So -- if this follows the scheme you were considering -- this should show that we can consider a superset of possible architectures, and more or less proves that the canonical architecture is already best.

Lastly; balancing... simply isn't an interesting problem.  If you require better than 10% matching, your thermal management is woefully, and dangerously, inadequate!  This should only ever be a design consideration, never an operating requirement!

You can add one more op-amp, outside of all the stages in parallel, to maintain total current equal to ref.  This amp can be arbitrarily precise, while the imbalance between stages can be gross (but managed) -- this could greatly simplify the circuit, say by using relatively large source balancing resistors and no per-FET driver at all, as long as the higher minimum (saturation) voltage drop is acceptable.  (Perfect for a high voltage CCS; for low voltages, you'd still want amp-per-FET.)

And you can always add thermistors to adjust local gate voltage, say; this would be a good idea if independent heatsinks are used.  Wire it up so the thermistor dominates over the FET's natural tempco.  Thermistors should be provided anyway to measure heatsink temp, and throttle down or disable operation if any one gets into a dangerous range.

Or, if the outputs aren't wired together, but they're for independent loads -- again, simply make each stage for the desired accuracy and that's that.

HTH,
Tim

[Vovk_Z]

And I simply don't understand why trying to make something work a little better causes such a controversy.

Because you tell us strange things - that comparators will be better then opamps (or precision opamps) in linear mode.

[hli]

Because no matter how well you pick your components perfect balancing would not be possible since  a tiny difference in threshold voltage between MOSFETs results in a substantial current mismatch . Other factors also effect the balancing like temperature and how well matched the other components are.

This is only true when you don't provide a feedback loop. If your basic operating principle is 'provide voltage X to the FET gate to achieve current Y', then yes, the current depends heavily on factors such as the gate threshhold voltage, temperature, and the phase of the moon (or whatever might incluence the FET too).
But this is not how the usual constant current circuit work. It uses the current shunt to create a feedback, and to keep the current at the same level regardless of the FETs parameters. There are just two factors (apart from the current set-point) which influence the actual current: the exact value of the shunt resistor, and the offset voltage of the driver OpAmp. Both can be correct for statically, when needed.
When you goal is to keep all FETs at the same temperature, you might need different feedback. Note that a FET with a slightly higher Rdson will reach a slightly higher temperature at the same current (because it just dissipates a little bit more power). If you need to, this can also be corrected for statically.
I suggest you just simulate the classical circuit, with lets says 3 FETs, in LTSpice - just use three different FETs (different Vgsth) and see how it behaves.

From what I understand from your (very small) explanations you want to achieve a similar kind of feedback ('I can control the gain'), but need just more components (controlling the driver gain introduced an error, and the comparators itself have an offset voltage). The usual problem with that is that each additional component in the feedback loop introduces a phase lag, so the loop becomes more unstable (and tends to oscillate). I suggest you too simulate yout circuit, and vary the component parameters a little bit to see which ones introduce errors.

And I simply don't understand why trying to make something work a little better causes such a controversy.

For one, no-one here understands how your cicruit is supposed to work. It would help to explain its operating principle in more detail (how does the feedback loop from the output current back to the FETs gate work).
Second, most people here know that your other premise "the classic curcuit does not work very well because it does not balance properly" is wrong - it works very well, and can be calibrated to arbitrary precisio if needed. They also that the latter is usually just pointless - the correct function of your system should not depend on achieving such precise balancing. (If you depend on balancing each FET with one degree C to each other, what happens if your room temperature rises by 2°C? What happens when you airflow gets disturbed by accumulated dust and one FETs just gets cooled a little bit less than the others? You need to have some error budget for such things, and it is much bigger than jst 1% imbalance between the FETs.
Yes, it might be an interesting exercise to see how good the balancing can be, but it is just a problem of accounting for slightly different shunt resistor values (and the offset voltage can be eleminated by using precision OpAmps).