Learn VHDL or Verilog for Power Electronic applications?

[Dmeads]

Hello!

I am interested in doing power electronics projects on SoC type chips and FPGAs. I want to do things like PWM, SPWM, Motor control, and simulate in real time using MATLAB/Simulink.

I am trying to learn verilog right now, and its going pretty well considering I have never taken a digital logic course.

The lecture Im watching on youtube said VHDL was designed for system design(high level), where as verilog was design for easy use with gate level design.

I don't have a ton of time right now, so would it be better for me to learn VHDL or Verilog for the projects im working on?

I have a tiny tiny bit of coding experience in MATLAB and Arduino but thats it, so its not like i would pick Verilog up easier due to it's c like nature.

Thanks!

[rstofer]

You're just going to start a language war!


If you understand Verilog (and I don't), then use it!  I started with VHDL so of course I'm going to say it is the best thing since sliced bread (it isn't).  But I have no real justification for selecting one over the other.

Some will say they hate the verbosity of VHDL, others will like it because the language is strongly typed.  And round and round it goes.

Just watch!

[OwO]

VHDL and System Verilog are both fine languages to use, just whatever you do avoid plain old verilog like the plague.