Author Topic: '161 vs '163 binary counters  (Read 1433 times)

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Offline MoriambarTopic starter

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'161 vs '163 binary counters
« on: April 27, 2021, 08:53:31 am »
Hi,
it's as simple as that: I have both '161 and '163 4bit synchronous counters (they were gifted to me by an electronics shop owner who retired, alongside a bunch of other stuff). I can't tell the difference though, they seem kinda the same. Can someone please explain?

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Online tggzzz

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Re: '161 vs '163 binary counters
« Reply #1 on: April 27, 2021, 09:34:06 am »
They are kinda the same.

The differences are stated in the datasheets. Look at the control signals.
There are lies, damned lies, statistics - and ADC/DAC specs.
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Offline MoriambarTopic starter

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Re: '161 vs '163 binary counters
« Reply #2 on: April 27, 2021, 09:44:17 am »
They are kinda the same.

The differences are stated in the datasheets. Look at the control signals.
hm looking at the waveforms it seems it's just the async clear, right? I had to compare printed sheets side-to-side lol
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Online tggzzz

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Re: '161 vs '163 binary counters
« Reply #3 on: April 27, 2021, 10:24:19 am »
You're welcome.

Training yourself to spot differences is a useful skill :)

You might like to have a look at the two titles, text descriptions, and pin descriptions in order to cement your ability to spot the keywords and concepts.
There are lies, damned lies, statistics - and ADC/DAC specs.
Glider pilot's aphorism: "there is no substitute for span". Retort: "There is a substitute: skill+imagination. But you can buy span".
Having fun doing more, with less
 
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Offline ledtester

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Re: '161 vs '163 binary counters
« Reply #4 on: April 27, 2021, 11:53:11 am »
This datasheet (which is for both chips) has the following to say about the two counters:

https://eater.net/datasheets/74ls161.pdf

Quote
...
The clear function for the DM74LS161A is asynchronous; and a low level at the clear input sets all four
of the flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs. The clear function
for the DM74LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop
outputs LOW after the next clock pulse, regardless of the levels of the enable inputs. This synchronous
clear allows the count length to be modified easily, as decoding the maximum count desired can be
accomplished with one external NAND gate. The gate output is connected to the clear input to
synchronously clear the counter to all low outputs.
...

 


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