+5V digital signal from 3.3V MCU - with ESD protection

[David Hess]

Quote from: simonlasnier on Today at 14:00:26

    And about the ESD protection I actually read online that a BJT would not need any protection as in case the voltage raises it will simply sink the current to ground, actually like a TVS diode would. Or did I miss something?


That pretty much covers it.  The gate oxide of a MOSFET is particularly fragile and must be protected from any excessive voltage or face catastrophic failure.  A MOSFET transistor could also be used in your application since the gate is not exposed.

David, that sounds like an excellent way to save money. Based on your experience, what model BJT, in which circuit would you suggest to the TO? For ESD severity let's assume standard human body model at 2kV. As a bonus, what would you suggest for a MOSFET-solution?

Do not misunderstand; it is not that bipolar transistors are immune to ESD damage, but that the MOSFETs are particularly susceptible at their gate lead.  So it is a good idea to protect any outside connection anyway to some extent depending on the application.  Good design practices for handing over-voltage, over-current, and radio frequency interference are usually sufficient.

In practice any transistor with a relatively large junction area protects itself, so parts with say a 200 milliamp collector/drain current rating or higher do not require any special protection against ESD, but it may still be desirable to protect bipolar transistors from reverse voltage; power MOSFETs have a built in body diode which does this for them.  Larger transistors with larger junctions are even better protected.

As far as what transistor to use, I would tend to go with the 200 milliamp 2N3904/2N3906 or 800 milliamp 2N4401/2N4403.  In the past I might use the 2N7000 n-channel MOSFET but there is probably a better modern part now.  A lot of old designs used the 2N2222/2N2907.  The exact part is not important.

[Zero999]

How about two NPN BJTs? That way there's only one type of transistor in your circuit.

Will also work.
My reason for choosing the NPN/PNP combo was that the output will stay at 0 V when the MCU/driver is powered off and when powering up.

It's just a question of whether the output resistor is pulling up (NPN version) or pulling down (PNP version). This makes a difference when powering up or down. The PNP output will be at 0 V during this time. The NPN version: I don't know.
Using two NPNs is redundant and unnecessary complexity to my mind (you can control the IO polarity in software).

You decide which behaviour is desired.

It won't make any difference. Both circuits will do that. If the MCU is unpowered, the first NPN transistor will be off, so the second one will be on, causing the output to be low. In PNP & NPN circuit, both transistors will be off, when the MCU is unpowered and the output will still be only 0V.

The NPN output can pull down hard, and the PNP circuit can pull up hard. The all NPN circuit has the advantage of having a simpler BoM and has the potential to be faster, but the latter is unimportant here.

[Benta]

It won't make any difference. Both circuits will do that. If the MCU is unpowered, the first NPN transistor will be off, so the second one will be on, causing the output to be low. In PNP & NPN circuit, both transistors will be off, when the MCU is unpowered and the output will still be only 0V.

The NPN output can pull down hard, and the PNP circuit can pull up hard. The all NPN circuit has the advantage of having a simpler BoM and has the potential to be faster, but the latter is unimportant here.

This is only true when you know from where the 3.3 V and the 5 V supply come from and how they ramp up/down. And we don't.

[Zero999]

It won't make any difference. Both circuits will do that. If the MCU is unpowered, the first NPN transistor will be off, so the second one will be on, causing the output to be low. In PNP & NPN circuit, both transistors will be off, when the MCU is unpowered and the output will still be only 0V.

The NPN output can pull down hard, and the PNP circuit can pull up hard. The all NPN circuit has the advantage of having a simpler BoM and has the potential to be faster, but the latter is unimportant here.

This is only true when you know from where the 3.3 V and the 5 V supply come from and how they ramp up/down. And we don't.

The same is true of both circuits. If the power supplies do crazy, unpredictable things, the outputs will do the same.

If what you're refering to is with the all NPN circuit, the output will go to 0.6V, before falling to zero again, if the 5V supply is gradually ramped up, then that is a disadvantage, but I wouldn't expect anything to happen with the rest of the circuit, at such a low voltage.

[Saimoun]

@Benta and Zero: Interesting conversation!! Thank you for the info it is great

Just FYI the +5V comes from USB, and the +3.3V from an LDO powered from that +5V.
I think the problem is more about the fact that the MCU GPIO will be floating at power up, and only a few micro/milliseconds later it can be pulled low.

I think I will try both circuits and see

[Saimoun]

So I tested the circuit with real components and everything seems to work fine.

BUT my idea was to use a TRS connector I already have on the board: the T (tip) connector was already wired to an input with a light load (about 100k), the R (ring) was unused, so I connected the 5V digital ouput to the R.

Without the filtering cap I get massive spikes on the T connector while the output is switching. Adding that 100nF cap reduces the spikes to about 400mV. The TRS connector's datasheet says there is 100Mohm isolation between the connectors.

Any idea how to reduce that cross-talk? Or maybe it is a terrible idea generally to use the same connector? 

Thanks

[harerod]

...

Do not misunderstand; it is not that bipolar transistors are immune to ESD damage, but that the MOSFETs are particularly susceptible at their gate lead.  So it is a good idea to protect any outside connection anyway to some extent depending on the application.  Good design practices for handing over-voltage, over-current, and radio frequency interference are usually sufficient.

That much I will accept, especially if it is understood that the transistor is backed up by other circuitry and and adequate layout. However, in my experience that "backup" would have to include ESD protection devices.
I also like your comment about other EMI scenarios. Emission testing usually being done first, is a great indicator for upcoming issues in the imission and ESD tests.

In practice any transistor with a relatively large junction area protects itself, so parts with say a 200 milliamp collector/drain current rating or higher do not require any special protection against ESD, but it may still be desirable to protect bipolar transistors from reverse voltage; power MOSFETs have a built in body diode which does this for them.  Larger transistors with larger junctions are even better protected.

A standard ESD test reverses polarity, will exceed ratings of most BJTs or MOSFETs, and inject charge into the rest of the circuit.

Alright, since we still don't know the numbers behind the TO's actual requirements (test level), we might as well wrap it up here. A recommendation would be to include ESD-protection devices at least in footprint and do ESD tests in different configurations.