32bit 1MSPS ADC to ESP32 project

[davegravy]

I don't have a specific question yet. I'm embarking on a project and about to spend a fair bit of $ so I would love to get a sanity check on my plan.

Background:
I have an EE degree from 15 years ago but haven never practiced in the field seriously (dabbled occasionally) so I'm a bit worried I'm going in over my head. Hope this is the right forum.

Concept:
The project concept is to learn about the LTC2500-32 ADC and see what it takes to get good performance out of it. I plan to interface with an ESP32 dev board. The ADC EVAL board is too steep ($) for me, I'm buying just the ADC chip.

Phase 0: Power it up, write some control registers, read some noise samples.
I'll be soldering to a DIP28 adapter and then building the circuit deadbug style probably but maybe solderless breadboarding (?)

For simplicity I'll be using Arduino framework. I figure I can use PWM to generate MCLK pulses at 1MHZ with a ~7% duty cycle. I'll probably be decimating by 22x on the internal filter to give me a data output rate of 44kHz. From the datasheet I think means the SPI SCK only needs to be around 44kHz so I assume the ESP32 with SPI library can keep up with that fine. I'll need to wait for the DRL line to go high and then start my SPI.transfer().

I'll stream the sample values read from the ADC via a wifi TCP socket to a pc running python which can plot my waveform, FFT, etc.

I have a decent 3ch bench supply, but no scope/logic analyzer  

Not worrying about supply regulation or anything at this stage, just want to read some noise (that's probably way out of spec).

Phase 1: Try to read an in-spec noise floor.
Get a proper low noise voltage reference for REF and quality LDOs for VDD and OVDD. Build a circuit to generate a low jitter MCLK.

Phase 2: Build an analog input buffer stage and try to read actual values from a signal generator.
Do a bunch of tests (frequency response, linearity, SNR, etc)

Phase 3: Fab a PCB and retest.

Phase N: Incorporate into a low power precision IoT soundlevel meter

[Gerhard_dk4xp]

Hi,
I don't think that you will get good performance when you start with a DIL28-Extender.
The LT2500 has good resolution, albeit far from 32 bits.
I have played with it in the context of a BeagleBoneBlack. I have made a little
home-etched board that contains the LT2500-32 ADC, 2* LT3042 low noise regulators
for analog & digital VCC, a negative regulator for the analog input driver, LT6655
reference and the ADC driver.
For the full bandwidth it takes 100 MHz SPI. During the measurement phase, the
SPI has to be quiet. The BBB has only 48 MHz SPI and i was unable to bring it
to work; the examples given did not fit the then-current Debian Linux.

Instead I used a small Xilinx-Coolrunner as a SPI-to parallel converter, then one
of the PRU coprocessors was fast enough to read 3 ADCs in real time.
I wanted 3 to be able to do 3-cornered hat cross correlation. That has been solved
otherwise in the mean time, so this here is somewhat orphaned now.
But I can setup the ADC from Laptop via network, Linux-ARM on BBB, dual port ram,
PRU real time processor, BBB pin I/O, and I can get samples from the ADC in the
opposite direction through the Xilinx CPLD.

Forget about solderless breadboarding, and without a scope life will be hard.

Cheers, Gerhard

[Siwastaja]

32-bit ADC on shoestring budget, some breadboard adaptor boards, random arduino/esp crap, and not even a hint about the actual project?

Are you kidding us?

What are you really doing, i.e., what are you measuring and what kind of resolution, accuracy and repeatability are actually needed? If we start here, I think we can help you better.

[Gerhard_dk4xp]

I think he is bootstrapping from Zero, probably too ambitious,
but that can be handled in a friendly way.

[davegravy]

Hi,
I don't think that you will get good performance when you start with a DIL28-Extender.
The LT2500 has good resolution, albeit far from 32 bits.
[snip]
For the full bandwidth it takes 100 MHz SPI. During the measurement phase, the
SPI has to be quiet. The BBB has only 48 MHz SPI and i was unable to bring it
to work; the examples given did not fit the then-current Debian Linux.

Hi Gerhard, thanks for the reply and your project sounds very interesting.

I will not be needing full bandwidth for this project, with a Downsampling Factor of 22 I'll only have an ODR around 44kHz which covers the full audible range. I may even double DF to 45. If I understand correctly from the datasheet on page 37 using Distributed Read this means the SPI clock can be significantly lower. From the timing diagram it looks like I need to read 32 bits over the course of DF MCLK cycles.

So if my MCLK sampling is 1MHz and DF is 22 my SCKA frequency can be 32/22 = ~1.5Mhz (or maybe a bit higher so that SCKA is quiet during conversion). I thought 1.5MHz was easily doable for ESP32. I don't understand why you needed 100MHz from the ADC datasheet.

Am I missing something or do you think Distributed Read makes things more practical for me and I can avoid needing an FPGA? FPGAs I think are quite power hungry and I'm hoping to use a low power MCU in the end. Hopefully even smaller than the ESP32.

I don't expect to get good performance with the DIL28-Extender but if you're saying it's unlikely I'll even get SPI comms functioning then I won't bother.

In terms of a scope I've been very tempted by the Riglol DS1054Z although if I need to inspect a 100MHz SPI clock like you say, that might be not enough bandwidth.

[davegravy]

32-bit ADC on shoestring budget, some breadboard adaptor boards, random arduino/esp crap, and not even a hint about the actual project?

Are you kidding us?

What are you really doing, i.e., what are you measuring and what kind of resolution, accuracy and repeatability are actually needed? If we start here, I think we can help you better.

Hi Siwastaja, excuse me as I kept my post concise. I didn't want to assume people wanted (or had time) to read a lot of background info, but I'm happy to share more! If you look at the last line of my original post I did drop a small hint 

The goal is a headless, low feature count, low power IoT sound level meter (SLM). Most instrumentation in this field is fairly power hungry and feature rich. Ultimately I'll be measuring sound from a microphone which may be something like an instrumentation grade microphone or possibly a MEMS microphone I'm looking to explore what is possible on the power-accuracy performance balance with newer technologies and see if there might be some opportunities. There are some digital MEMS microphones with I2S output I've looked at that simplify things a lot but are somewhat limiting in a few performance areas.

At this point I don't know the accuracy and repeatability requirements exactly. SLMs are governed by a fairly rigorous IEC standard (61672) and a lot of contracts demand compliance to this even though it is overkill for some applications. I'm not necessarily targeting compliance but I'm keeping it in mind. I think it's fair to say beyond dynamic range that the instrument can operate over, the standard is more limiting to microphone selection than ADC. For frequency response, for example, the standard has tolerances as tight as +/- 1.1dB which I think is easy for a good ADC.

Where the ADC is concerned it's a matter of the dynamic range and input gain to place that range usefully for the sensor used. With a high DR I can target applications where ambient sound levels are very low (rural, remote environments) and where there are loud events (like construction or blasts from a mine). I may give up on DR and noise floor expectations and limit the use to urban high ambient environments. I don't need 32bits in even the most demanding situations  but what I like about the LTC2500 is it seems to have good power consumption performance for a given dynamic range and the ability to fairly easily tradeoff one for the other using only digital control.

Supposing I care less about DR, I can reduce Downsampling Factor (DF) from 22x to 1x and reduce MCLK by the same factor and get a good power consumption drop for the same output data rate. Admittedly I haven't thought too far about aliasing and the frontend filtering implications of this. Maybe the power saved would be paid for in op amps of a high order filter.

Does that help provide some insight? My employer may decide to fund this as a larger project eventually but they usually like to see some groundwork and I'm happy to put some of my own money at it as a fun learning experience. But if it's too ambitious then please say so and I'll empty my digikey shopping cart and walk away slowly

I've done a lot of reading in the last few days on this and at some point soon I need to actually start working with my hands because if I know myself I'll lose interest otherwise.

[Siwastaja]

Well sure, now it starts sounding more realistic. This should be doable with bog standard 16 bit audio ADC, I think.

Still, even in "just" 16-bit audio, proper layout, groundind, shielding etc. are important, as evidenced by computer audio devices which emit all kinds of annoying noises caused by spiky CPU power consumption.

Every bit roughly doubles the challenge. So you see why I was suspicious of the 32-bit ADC, seeing that even 16 bits is a challenge. If the signal level varies between -1..+1V, in 16-bit system you measure 0.03mV steps. Need to be careful with small ground shifts etc. But in a 32-bit system, that step would be 0.0000005 mV!

Start prototyping and see how it goes?

[jmelson]

Sanity check??!!?? 32 BITS??!!??  The LSB on that device is 1.1 x 10^-9 V!  That's 1.1 Nano-volts!  I suspect you will be lucky to get 16 good bits out of it with ordinary construction techniques and components.  Don't use any resistors, they are noise sources.
Jon

[rstofer]

There are some useful links in this thread - same topic, different application.

https://www.eevblog.com/forum/beginners/help-figuring-out-voltage-divider-for-adc-input/

Using an external ADC is probably wise since the 16 channel internal ADC only comes with a 6% accuracy spec.  It's hard to get precision capacitors in silicon.

[davegravy]

Well sure, now it starts sounding more realistic. This should be doable with bog standard 16 bit audio ADC, I think.

Still, even in "just" 16-bit audio, proper layout, groundind, shielding etc. are important, as evidenced by computer audio devices which emit all kinds of annoying noises caused by spiky CPU power consumption.

Every bit roughly doubles the challenge. So you see why I was suspicious of the 32-bit ADC, seeing that even 16 bits is a challenge. If the signal level varies between -1..+1V, in 16-bit system you measure 0.03mV steps. Need to be careful with small ground shifts etc. But in a 32-bit system, that step would be 0.0000005 mV!

Start prototyping and see how it goes?

The challenge with 16 bit is it has a maximum dynamic range of 96dB. I'm aiming for 120dB ultimately, understanding I'm unlikely to get that initially with first prototypes (solderless breadboard) but can "grow" into it with successive design iterations.

24bit would suffice but devices I've looked at are either unavailable (covid supply chain), are too high power, or too low sample rate.

It's an expensive ADC but I was thinking I can carefully desolder it to move it between board design iterations. There's a lot of pins but I was imagining carefully heating the PCB in a toaster oven so the components drop off at solder melting point. Let me know if this is fanciful thinking.

In terms of ultimately achieving 120dB dynamic range, what is it likely to take beyond sticking as closely to the board layout and component type selections that AD uses on the EVAL board?

FWIW the microphone I want to test with this has a dynamic range of 137dB re 20uPa.

[Siwastaja]

ADC resolution is least of the challenges. Getting noise down and good linearity for 24 bits ENOB is a massive challenge. Buying a 24- or 32-bit ADC is the easiest part, designing and laying out the whole circuit is the problem.

For example, I couldn't do it or it would take a year of learning and testing. I'm sure there are a few people on this forum who could, though. But just few.

[davegravy]

The eval boards have been optimized by the manufacturer to have good performance, right? Their schematic and layout design files are available so I thought I could get part of the way there by staying as true to Analog's reference design as possible.

Maybe that's easier said than done.

[Siwastaja]

That's a good start, especially if your application happens to be similar to that eval board.

Sometimes eval boards are design failures. But you could think when talking about a 32-bit ADC, someone would have done good work with it. It's not 100% guaranteed though.

But the whole signal path matters. Obviously, if you happen to have an IC with good analog performance, outputting differential signals with suitable drive impedance for ADC, and suitable signal ranges, the amount of design you need to put in is greatly reduced compared to the case where you need to add amplification, for example.

The significance of power supply noise is often overestimated by novices (in usual gadgets, it doesn't matter), but this is a case where it really matters. Same about shielding.

[davegravy]

The significance of power supply noise is often overestimated by novices (in usual gadgets, it doesn't matter), but this is a case where it really matters. Same about shielding.

Given my application is concerned with the audible range of sound and any spectral content below 20Hz will be filtered via DSP, do I have to concern myself with <10Hz voltage reference noise?

The recommended voltage reference for the LTC2500 is the LTC6655 which is quite power hungry. From what I can tell there is 1-10Hz and 10-10kHz noise performance, and power is a tradeoff with noise. Higher frequency noise can be fairly easily filtered with an output capacitor but this is of course impractical for low frequency noise.

I'm considering the LTC6652 which is about 10x reduced quiescent current and 10x higher noise. Also my project will be battery powered if that matters (no line noise)

[Siwastaja]

Well, since this isn't just "sounds good" HiFi project, but a measurement instrument, you might be concerned about low frequency noise (at the extreme, called "drift").

Is it OK if it reads 57dB one day, but after a day, week or year, it shows 58dB for exact same actual SPL?

For a HiFi audio project, this wouldn't matter as the listener would adjust volume to their preference anyway.

[davegravy]

Good point. In the industry we are expected to calibrate before each set of measurements. The calibration corrections we see are usually on the order of 0.1dB however, not 1dB. And that's over months not days of drift. I'll have to check what the applicable standard says about stability.

[davegravy]

I'm looking at power consumption. It would be great if someone could validate that I understand this correctly.

The primary sources of power dissipation are, in order:

• ADC Driver
• ADC
• VREF regulator quiescent
• Other voltage source regulators quiescent (Rails for driver, ADC supply)

The ADC driver I'm using (LTC6363) appears dominant, at least for my preliminary design, and it varies significantly based on the amplitude of the input signal and the size of the external resistors used to form the driver gain. Increasing the size of the external resistors increases the noise floor, so this is a tradeoff between power consumption and noise floor.

See attached results from my simulation of the LTC6363.

In summary I'm predicting:

• ADC Driver - 9 to 32mW
• ADC @ 1MSPS - 19mW
• VREF regulator (ADR4550) - 5mW
• Other regulators (LT1763) - <1mW

If that sounds roughly correct then great! Hopefully I'm not missing anything big.

[srb1954]

Sanity check??!!?? 32 BITS??!!??  The LSB on that device is 1.1 x 10^-9 V!  That's 1.1 Nano-volts!  I suspect you will be lucky to get 16 good bits out of it with ordinary construction techniques and components.  Don't use any resistors, they are noise sources.
Jon

Also don't use a PCB.

At that sort of resolution you would even have to be concerned about the thermal noise in the Cu tracks on your PCB.

[davegravy]

Sanity check??!!?? 32 BITS??!!??  The LSB on that device is 1.1 x 10^-9 V!  That's 1.1 Nano-volts!  I suspect you will be lucky to get 16 good bits out of it with ordinary construction techniques and components.  Don't use any resistors, they are noise sources.
Jon

Also don't use a PCB.

At that sort of resolution you would even have to be concerned about the thermal noise in the Cu tracks on your PCB.

Sorry if it wasn't clear but while I'm using a 32bit IC I need an ENOB much lower. Availability of ICS that have integrated digital filters is poor so I'm using what's available. I did find a 24bit chip which is pin compatible, the LTC2512-24.