There are two glaring issues with this circuit. The first is that the 1000uF capacitor is massive for this circuit. The problem is that electrolytic capacitors have a relatively large leakage current that needs to be taken into account. This limits how large you can go in timing resistor value.
The second problem is that the internal NPN discharge transistor has a limited current carrying capacity. To limit the current (and protect the transistor) you should have a low value resistor in series with the discharge pin.
This is largely nonsense, and not very helpful to the OP.
As I imagine you are aware, the output pulse width for a 555 in monostable mode is given by:
t = RC ln(3)
where t is in seconds, R is in ohms and C is in farads. ln(3) is roughly 1.1, so for a 1000uF capacitor and a 100k resistor, the pulse duration will be:
1.1 x 0.001 x 100000, which is 110 seconds.
This is perfectly suitable as a maximum value for a variable delay timer of the sort being tried. The 3.3k resistor given in the schematic would give a maximum of around 3.6 seconds, which is maybe a little brief.
As for the capacitor leakage current, I charged a cheap Chinese 1000uF capacitor to 9V and after 60 seconds the voltage had dropped by 0.02 V. I really don't think that's going to be an issue in this circuit.
Lastly, 555 timers have internal limits on the collector current for the discharge pin. You aren't going to damage it by not using a discharge resistor.