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74HC390: Ripple Counter is Counting Rubbish

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EEVblog:

--- Quote from: LateLesley on May 03, 2019, 10:21:06 am ---i'll add to the "not a stupid question" crowd. I was once told, "The only stupid question, is one you already know the answer to."

As for the problem, I wonder if we are actually seeing intended behaviour?

If we follow the sequence :-
    Q3 Q2 Q1 Q0
0 - 0  0  0  0
1 - 0  0  0  1
2 - 0  0  1  0
3 - 0  0  1  1
4 - 0  1  0  0
5 - 0  1  0  1
6 - 0  1  1  0
7 - 0  1  1  1
8 - 1  0  0  0
9 - 1  0  0  1
10 - this is where it resets to 0, as it''s a decade counter.

So as you can see Q1 Q2 and Q3 won't divide into perfect square waves, as there times when they are off for longer. like Q1 for 8,9,0,1 it will be off, giving a longer gap in the waveform. The same applies to Q2, it's off for 6 counts, but on for 4. So I would actually count out each step, and see if you are seeing intended behaviour for that chip.

--- End quote ---

But we aren't seeing that on the scope. It is supposed to be exactly like the timing diagram.

MrAl:
Hello there,

The output from an opto coupler has very slow rise and fall times unless it is made specifically for digital logic.
As the output ramps up during the rise time, it eventually gets close to the threshold voltage of the logic gate input and then the always present noise can go above and below the threshold voltage several times before the ramp finally gets high enough to overcome the noise completely and then provide a stable logic state.  Before it gets past the noise it can clock a counter several times or just a few times just on that one rising or falling edge alone, and that will mean we will see a varying response from the counter chip which means we get garbage out.

This is a very common problem even for circuits that dont use opto couplers.  Many types of signals are slow rising and falling and so they need to be cleaned up before presented to any type of logical counter.  Typically we see a Schmitt Trigger gate being used for this purpose.  These kinds of gates have a wider threshold region which means the noise gets lost in between the upper and lower threshold voltage levels.  This means we get a nice clean digital signal out of the gate which means the clock input to the counter gets a nice clean signal.  After that everything works as expected.

Alternately you could look for an opto coupler that has a digital output that is made for the digital logic family you are using.

MikeMike:
Noticed that the optocoupler data sheet says "A 0.1μF bypass capacitor must be connected between pins 8 and 5" (aka Vcc and GND). Doesn't appear to be one on the breadboard. Adding one might help.

donmr:
Reducing the pullup will speed up the rising edge, but it will also slow down the falling edge!  A schmidt trigger is the right answer.

Dave also didn't address the series 270 ohm resistor.  You don't want that.

Peabody:
The thing to do is to leave the HC390 circuit exactly as it is, but drive the input from a good, fast signal, and see if it still misbehaves.  Well, that's what I would do.

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