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| 74LS14 testing circuit pls |
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| Chriss:
In the first version I had that with the switch, after I found that good gate I connected also my photo interrupter to the 74LS14 good gate and made the measurements... I know it is hard to remote troubleshooting... I was thinking also about the LM339 to use, but I found more simple to use a 74LS14 in my circuit than the LM339. I tested in my circuit that one IC 74LS14 which have a good gate and it is doing the job well. I also connected it to my uC and started to count the triggered signals and works great. I don't know, maybe I will give a try to another IC but now from the 74HCT version and something not from the year '85. :-DD I just was wondering about my situation with this IC's because I was playing before also whit such of IC's and I never had a burnt one or situations like now, except if I repaired some electronics with a bad Schmitt trigger... So, back to the situation, I assume more or less my schematic shouldn't kill the IC's. Maybe that version where I connected the LED to the IC. But I have also a bad IC on which was the LED not connected. I will try to get a new ic but now one from the 74HCT version and make a new test.. I don't know, maybe I messed up something. Just one more question: If I don't connect the unused pins to gnd, can that kill the IC? |
| rstofer:
Some of MY rules for logic (regardless of family) * Apply Vcc and Gnd to the proper pins with short leads from the PS * Add 0.1 ufd capacitor between Vcc and Gnd at EVERY chip and keep the leads as short as possible. There are sockets with built-in capacitors - that is short! * Always pull inputs high and switch them low. The size of the pull-up resistor depends on the logic high threshold and the pin input current. If I don't care about power consumption, 1k is the right answer. * Never pull a load high, always pull it to ground. This is important for TTL and less so for CMOS but I do it that way anyway. |
| rstofer:
--- Quote from: Chriss on April 13, 2018, 09:35:44 pm --- Just one more question: If I don't connect the unused pins to gnd, can that kill the IC? --- End quote --- It can be for CMOS. You need to treat the inputs and outputs properly. You can pull inputs to a solid ground but I would never pull them to a solid Vcc. I ALWAYS use a resistor to limit the logic high current (others will have a different opinion). ALL inputs on ALL devices need to have some kind of connection. Up or down, your choice but they can not be allowed to float. Outputs: Never pull an LED up, always pull it down, read the datasheet for maximum output current - both high and low. Connect the resistor between Vcc and the LED anode, connect the LED cathode to the output pin. ETA: You can tie multiple inputs to the same pull-up resistor but you have to make sure the resulting pin voltage is higher than the logic 1 threshold with all inputs sinking their maximum logic high input current. |
| TomS_:
--- Quote from: Ian.M on April 13, 2018, 08:45:53 pm ---74ACH..../74AHCT.... are excessively fast, which causes problems if you have long wires or don't have good grounding and decoupling --- End quote --- Sorry for the hijack, but this is burning a hole in my understanding - which was that the AHC/AHCT versions "simply have a lower propagation delay" (thats the way TI marketing material positioned it anyway). If the HC/HCT versions are a bit slower propagation wise, how does an input transitioning an output a bit quicker cause such significant issues? Or perhaps I have missed/do not understand another detail... |O Re using xHCT parts, I have been looking to stock these specifically because so many microcontrollers and other logic devices seem to be 3V3 parts these days, particularly at the mid-high end, and the xHCT parts are more compatible due to lower logic high requirement. So its more or less about stocking parts which can be as universal as possible. Thanks! |
| Ian.M:
Its all down to risetimes and load capacitance. The faster the risetime, the bigger the current spike drawn from Vcc or Gnd to charge or discharge the load capacitance when an output switches and the greater the resulting threshold shift experienced by other gates on the same chip caused by the disturbance at its supply pins. Then its a matter of noise levels on the inputs and the probability that the threshold shift will momentarily erode the logic input threshold margins enough to cause a glitch. Its a square law effect - the current spike amplitude increases in proportion to the speed of the transition, but its duration also reduces proportionately, so a 20% reduction in risetime makes it 44% harder to decouple the supplies adequately and provide a reliable ground (stiff enough at DC and low enough impedance up to an equivalent frequency to double the rise time) With very fast logic you get into the situation that you need to source terminate longer lines to control the risetime to tame the spikes. |
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