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88E1512 PHY can not reach Gigabit on FPGA

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lk.dgironi:
Hi all,

I'm working on a custom board that needs Gigabit Ethernet.
It's based on the Tang Primer 20k board, so the GW2A-LV18PG256C8/I7 GoWin FPGA.
As PHY I've try the Marvell 88e1512.
I'm using the Alex Forencich verilog-ethernet core.
Previously I was using ksz9031 but I have auto-negotiation problem on gigabit if the ethernet cable is disconnected after the PHY has been powered on (no luck asking here https://forum.microchip.com/s/topic/a5C3l000000BoLNEA0/t390661), so I've try moving to 88e1512.
The problem is that with this last one I can't event reach the Gigabit.
FPGA synthesis is the same, so it's not a code problem.
Setting my PC PHY at 100Mpbs without auto-negotiation makes the board works, but the communication is not smooth, I found some packets loose.
Note that I don't use MDIO and MDC, cause the FPGA talks in pure RGMII to the PHY, so I'm not able to se registers and check for internal PHY errors.
My 88e1512 it's based on other FPGA boards (like the PicoZed).

The problem behaviour:

At 1Gbps or auto-negotiation enable on PC, I see "cable connected" at 1Gpbs but every packet send by the FPGA PHY is dropped (can't see packets on Wireshark), LED1 88e1512 is off, LED0 88e1512 if on.
At 100Mbps Full Duplex with auto-negotiation disabled on PC, I see "cable connected" at 100Mpbs but most of the packet send by the FPGA PHY are not dropped, LED1 88e1512 is off, LED0 88e1512 if blinking.

While the ksz9031, no packet dropped by the PC. At 1Gbps or auto-negotiation enable on PC it works at "first boot". When cable is disconnected LED1 and 2 goes off and does not negotiate untile next power off - the RST signal does nothing. At 100Mbps Full Duplex no more problem of negotiation even after the cable is disconnected.

I'm lost now, don't understand why does not negotiate. I think is something about the magnetics but I don't know.

radiolistener:
I'm used Alex Forencich core for ethernet, it works well and don't needs to read PHY register to detect current link speed, it can do it automatically by measuring clock. It automatically switch between 10/100/1000 and works very stable. If you have some issue with gigabit link, probably there is some issue with clock or phase. Another possible issue is non standard packet setting. I have the same issue when tried to reduce interframe gap or preamble between packets

lk.dgironi:
Thank you radiolistener.
Indeed I don't think it's a firmware problem, I think it's something related to the board layout or schematic. As a matter of fact the KSZ9031 works well.
The MDIO/MDC can be useful to get the PHY register and so to understand the errors if any happens, but I'm not using them too.

radiolistener:

--- Quote from: lk.dgironi on September 27, 2023, 10:09:18 am ---Thank you radiolistener.
Indeed I don't think it's a firmware problem, I think it's something related to the board layout or schematic. As a matter of fact the KSZ9031 works well.

--- End quote ---

it is possible that some data lines between FPGA and PHY have different electrical length and as result different phase delay. It may lead to error in data transfer. If you know phase error for each line you can provide that information for synthesis and it will add proper delay.

Also you can play with clock phase, try to add some delay, may be it can help to latch correct data. Usually PHY chip has configuration for clock delay, it can be selected with proper signal combination during PHY reset. May be you're failed to setup proper clock phase configuration. It can work at 10/100M, but will fail at 1000M

lk.dgironi:
Thank you,

All below about the NEW board and the 88e1512.

I've checked the track in my board, find below the track in mils


Length on TP20k   Length on Dock   Signal name   Total length   Diff from the biggest
           
388,12            1574             TX_EN         1962,12        835,23
275,29            1574             TXC           1849,29        948,06
1223,35           1574             TXD3          2797,35        0
473,58            1574             TXD2          2047,58        749,77
1069,26           1574             TXD1          2643,26        154,09
319,08            1574             TXD0          1893,08        904,27
                                                 
1329,60           2401             RX_DV         3730,6         83,28
1412,88           2401             RXC           3813,88        0
833,36            2401             RXD3          3234,36        579,52
639,87            2401             RXD2          3040,87        773,01
735,89            2401             RXD1          3136,89        676,99
560,73            2401             RXD0          2961,73        852,15

Also I've found using the Analytic in my FPGA development environment that the the alex core trigger FCS error on each packet received (at 1Gpbs).

Does that mils makes the difference? Or there's something I'm missing (like the magnetics ora anything else).

Note that the "speed" signal in the alex core is correctly set to 1(100Mpbs) when my PC has 100Mpbs full duplex setted, when it's auto-negotiation speed is set to 2 (1000Mpbs). So the PHY does the negotiation in the proper way... I think :)

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