8x1:2 Multiplexing and also level translation?

[smoothVTer]

I need to multiplex two parallel 8-bit data streams from difference sources onto a single  8-bit bus for input to a video display.    I've found a nice IC seemingly intended for this purpose:    http://www.idt.com/products/memory-logic/bus-switch/50v-quickswitch/qs3390-high-speed-cmos-quickswitch-168-multiplexer

The only problem is,  the first data stream uses 3.3V logic levels.   The second data stream uses 1.8V logic levels.      The input to the display must use only 1.8V signals.   

The datasheet for QS3390 above mentions that it can be used for 5.0V to 3.3V level translation, but doesn't specify in the datasheet how this is achieved.   So, how is this achieved in practice?      Second:   how would I know or find out if this IC and others like it could possibly support 3.3V to 1.8V translation as well?   Or am I going to have to get a separate 3.3V-to-1.8V level translator IC?   

Thoughts on the simplest solution?

[Marco]

The datasheet for QS3390 above mentions that it can be used for 5.0V to 3.3V

They probably just mean you can use the 5v logic to switch, connecting the output to 0 or 3.3V at the input with a pull up/down to get 3.3V logic. Not a good idea for very high speed signals.

How fast are your signals?

[smoothVTer]

So to test this setup out:

I have Bus 1 @1.8V
I have Bus 2 @3.3V

I power the Mux from a 3.3V supply

On the output of the mux I pull the outputs to a 1.8V rail with a resistor.

Is that correct? 

[rstofer]

There's an app note (AN-11) that explains how the 5V to 3.3V level shifting is done.  Basically, it amounts to limiting Vcc for the MUX.

http://www.idt.com/document/apn/11-5v-and-3v-conversion-zero-delay

No suggestions on the 1.8 vs 3.3 thing.  I don't know if the dropping diode can be changed to accomodate the lower voltages or not.

[edavid]

I suggest using 4X SN74LV4T125.

http://www.ti.com/product/sn74lv4t125/datasheet

[smoothVTer]

@eDavid:

This!  Exactly, thank you!

I spent several hours today on Digikey trying to find something similar but there are a dizzying array of Mux's, De-Mux's in all sorts of configurations, only maybe 50% of which matched what I was expecting. 

Using the SN74LV4T125, here's what I am able to come up with:



Does this capture the intent of your suggestion?   If yes, thank you.   The only thing I am worried about in this system is the rise-time stretching effects of the 1.8V side.   I'm using a protocol called BT.656 which is an 8-bit parallel bus clocked at 27MHz, giving a clock period of about 37ns.     Is there a way to estimate what the rise-time penalty hit will be using the data from the datasheet?   I see threshold levels but not really much in the way of how rise-time is affected on the output side.  I understand that without a defined output capacitance, this question is not possible to answer directly, but short of putting the system together and measuring with a scope is there anything else I can do to predict rise time and/or output waveform degradation?

[edavid]

Does this capture the intent of your suggestion?

Yes!

The only thing I am worried about in this system is the rise-time stretching effects of the 1.8V side.   I'm using a protocol called BT.656 which is an 8-bit parallel bus clocked at 27MHz, giving a clock period of about 37ns.     Is there a way to estimate what the rise-time penalty hit will be using the data from the datasheet?   I see threshold levels but not really much in the way of how rise-time is affected on the output side.  I understand that without a defined output capacitance, this question is not possible to answer directly, but short of putting the system together and measuring with a scope is there anything else I can do to predict rise time and/or output waveform degradation?

It seems like it should be fast enough.

If you run the clock through the same kind of buffer, that will maintain your setup and hold timing margins.