ADS8584S Timing Diagrams Questions

[SethGI]

Hi everyone,

I'm reading through this datasheet, and I got a bit confused by some of the timing diagrams:

https://www.ti.com/lit/ds/symlink/ads8584s.pdf?HQS=TI-null-null-digikeymode-df-pf-null-wwe&ts=1601232455191#page=26&zoom=100,0,689

On Page 43, it says data is available at the falling edge of ~CS/~RD (Event 3). But, the timing diagram doesn't seem to align like that. What am I missing here? Would I be able to sample at the falling edge of ~CS/~RD, or would that result in some incorrect data? If anything, it looks like data is available at the __rising__ edge.

Also, I don't quite see how I would do multiple consecutive reads (at the full 300KS/s). Normally I would expect to just leave the CONVST pins high, and it would just spit out data at the sample rate. It doesn't show that happening in timing diagrams (it's always one sample per channel, followed by another CONVST pulse. Would I have to manually pulse CONVST to sample? That seems wrong...

Any insight appreciated!

Thanks,
Seth