NTSC Composite Video Circuit DC Bias

[Dark Druid Nergal]

Hi all,

I've been researching how to generate an NTSC-compatible signal with digital logic. I've successfully generated a black and white signal in software with a microcontroller and basic resistor DAC and am now looking into generating a color signal. During my research, I came across this circuit (schematic in the attached PDF) as well as a series of YouTube videos detailing its design. I understand the basic principle; the circuit is counting up at a multiple of the colorburst frequency (3.57 MHz) and triggering synchronization pulses or outputting pixel data at the appropriate ticks of that counter. When outputting pixel data, the circuit is using 4 bits to generate 1 of 16 luminance values, and 4 bits to select between 15 pre-shifted 3.57 MHz waveforms (and 1 ground connection for grayscale), allowing for 256 colors corresponding to every bit pattern from 00000000 to 11111111. The signals are then mixed and sent to the final composite output.

My question is about the voltage levels in this circuit. From my research and what I did with the microcontroller, it's my understanding that a composite video signal should have a peak-to-peak voltage of 1V. For hobbyist projects, this usually takes the form of 0V representing a sync pulse, and anything from 0.3V to 1.0V representing increasing levels of brightness. In this circuit, I don't see how it would be outputting a black color with a binary pattern of 00000000, for example. With everything set to 0, that means all the luminance selections are being driven low, and the multiplexer for the chrominance is selecting the connection straight to ground. With everything being driven low in this circuit for this bit pattern, shouldn't the final composite output be 0V? And if that's the case, wouldn't this cause the TV to interpret a sync pulse instead of the black level?

I asked the designer about this on his video, and he replied saying that the voltage divider at the end of the circuit biases the voltage up to 0.3 V, but I'm not entirely sure how. Can someone explain this to me?

[Benta]

A few dollars will bring you the answer:
https://www.amazon.com/Video-Demystified-Handbook-Digital-Engineer/dp/1878707361
Best book on video ever written.

Deriving Vsync and Hsync from the color burst clock is the worst idea ever. The color clock was intentionally chosen to NOT be a harmonic of either.

[edavid]

With everything set to 0, that means all the luminance selections are being driven low, and the multiplexer for the chrominance is selecting the connection straight to ground. With everything being driven low in this circuit for this bit pattern, shouldn't the final composite output be 0V?

Doesn't the CSYNC signal being high pull the output up to 0.3V outside of sync?

[edavid]

Deriving Vsync and Hsync from the color burst clock is the worst idea ever. The color clock was intentionally chosen to NOT be a harmonic of either.

This is incorrect for NTSC:

3579545 Hz color subcarrier / 227.5 = 15734 Hz line rate
15734 / 525 = 29.97 Hz frame rate

[BrianHG]

Deriving Vsync and Hsync from the color burst clock is the worst idea ever. The color clock was intentionally chosen to NOT be a harmonic of either.

This is incorrect for NTSC:

3579545 Hz color subcarrier / 227.5 = 15734 Hz line rate
15734 / 525 = 29.97 Hz frame rate

Correct under broadcast quality conditions, or digitally generated video conditions like you see on old game consoles or higher quality capable computers like the Amiga home computer where a few NTSC output devices had near or total broadcast quality video capabilities.

Because of the narrow band of the 3579545.45... Hz needs to be kept exactly there and the varying speed of analog video tape player's spinning video head, there is a timing shimmering effect between the color burst phase and the sync just to the left of it when viewing a non-TBC'd analog video tape playback on your oscilloscope.  But if I were to explain all the details here on what's going on, we'll have a 5 page brief on the subject.

Yes, with a 4 bit dac & rom (I used a CPLD which game me the sync counter logic as well), I once in the past mad a color video NTSC output device.  To preserve the most possible out of my precious 16 dac levels, for the sync, I had a separate 5 digital output from my CPLD based generator which pulled down the output of my dac below the black level to achieve the lower sync voltage.


For your jellybean circuit, I dont get your issue.  You have a 4 bit luma dac, IE 16 grey shades.  A separate bit for black than black, IE the sync level, IE your sync generator.  Another bit for a capacitively coupled superimposed chroma signal and another bit even weaker capacitively coupled color burst to any level the video output is at like the chroma, but just weaker.  So, what's wrong?

It almost looks like an Atari 800 video output generator circuitry.

There is no such thing as a DC bias in an NTSC video signal.  It supposed to be AC coupled through a large cap when sending it out of a video connector.  It is the job of the TV on the other side to find the true black level by clamping down the signal during the time position of the color burst, the average voltage level it sees there is made to be the reference black 0v.  Everything after above that point becomes whiter and whiter...

[Dark Druid Nergal]

Thanks for the responses everyone. I think edavid was exactly right here and I was mis-analyzing/misinterpreting the behavior of the circuit. I didn't see how the circuit depicted in the schematic was maintaining a baseline voltage of 0.3V while all the luma and chroma bits were low, but I overlooked the input of the CSYNC signal. In concert with the TV's impedance, while CSYNC is high it must be keeping the voltage at the minimum threshold for black, and then pulling it down to the sync level whenever the horizontal or vertical sync pulses are active. I feel a bit silly now, but thanks for pointing it out.

[Terry Bites]

The output level should be 2Vpp unloaded or 1Vpp when terminated with 75R. To achieve this the ouput impedance is also 75R.
You can set your sinc tips to ground but the monitor circuitry will fix any deviation from that with its own internal DC restore function.
 Have a read.....