Am I doing this right? VGA signal buffering and termination

[HwAoRrDk]

I'm adapting an existing design that outputs a VGA signal from a Raspberry Pi Pico RP2040 microcontroller. The existing design uses a simple 390/780Ω resistor DAC to output 2bpp per each of the RGB signals essentially straight from the microcontroller. The H/V sync signals also come straight from the MCU. While this probably works, I don't believe this is a great way to do things, because of the currents having to be sourced by the MCU. By my calculations (assuming typical 75Ω termination load) it's potentially having to source about (9+4)×3 = 39mA total for the RGB signals, plus whatever the sync signals are having to source. While the RP2040 specifications give no specific per-GPIO pin maximum, they give an absolute maximum of 50mA total for the entire chip, and IMO we're getting uncomfortably close to that. Additionally, the H/V sync signals will only be 3.3V, which technically satisfy 5V TTL logic levels, but I doubt it would take much to make it flaky.

So, I've decided to modify the design and add some buffering to drive the VGA signals. But I don't think I really properly understand transmission lines and termination, so I'm not sure I'm doing it right.

I'm going to use the TI THS7316 3-channel video buffer chip to drive the RGB, and a 74LVC17 buffer to drive the sync.



The THS7316 has a gain of 2V/V and an input offset of +140mV, plus an internal 800k pull-down in each input. So, I've adjusted the resistor DAC values and added a lower divider resistor to compensate so that the peak signal level into the buffer is 560mV, which I think should end up with the requisite 700mV p-p output at the other end. This is my simulation. Is this all okay? One thing I'm concerned about is whether I'm making the DAC resistors too high-impedance (5k/10k) and whether I should lower their values.

But, one thing I've seen recently makes me question whether I'm doing things correctly, and whether I should have 75Ω series or parallel source termination of the RGB. I thought I'd look at some publicly-available schematics of old graphics cards (e.g. here (p9) and here (p11)) to see how they drive signals, and... they're using parallel source termination?!? I always thought parallel termination was for the receiving end? Are they doing that because of the characteristics of the signal generated by the GPU IC, and it's not necessarily applicable to my scenario? Or am I doing it wrong? I'm confused.

[Benta]

Your schematic is right. The 75 ohm series resistor at the buffer output set the output impedance to 75 ohms as required for feeding into the cable.
The receiving end has 75 ohm shunt rsistors, giving it an input impedance of 75 ohms.
So you have perfact mstching all thought the transmission line.
Downside is, that you need 2x voltage gain to compensate for the loss in the matching resistors.

This supposes that the output impedance of your buffers are close to zero, and the input impedance of the receiving amps/inputs is high. But that's almost a given with modern amps.

[HwAoRrDk]

Downside is, that you need 2x voltage gain to compensate for the loss in the matching resistors.

Ohhhh. Now I get why the THS7316 has a gain of 2x, because they assume that you're going to be adding a source impedance of 75Ω as well as a receiving input impedance of 75Ω, and that halves the voltage at the receiving end. I didn't properly understand why they were doing that before - I wondered why a buffer driver needed to amplify the signals. Now it's clear.

This supposes that the output impedance of your buffers are close to zero, and the input impedance of the receiving amps/inputs is high. But that's almost a given with modern amps.

The datasheet of the THS7316 does list an output impedance of 0.5Ω, so yeah, very low as to almost be insignificant I guess.

I still don't understand the parallel source termination the example graphics cards are using.

[David Hess]

But, one thing I've seen recently makes me question whether I'm doing things correctly, and whether I should have 75Ω series or parallel source termination of the RGB. I thought I'd look at some publicly-available schematics of old graphics cards (e.g. here (p9) and here (p11)) to see how they drive signals, and... they're using parallel source termination?!? I always thought parallel termination was for the receiving end? Are they doing that because of the characteristics of the signal generated by the GPU IC, and it's not necessarily applicable to my scenario?

If they used current output DACs, which would have been faster, then the source termination would be in parallel instead of series.  And that is exactly where is shown here for this current output VGA RAMDAC.

[HwAoRrDk]

Ah, I see. I did a bit more searching, and it seems it's common for VGA outputs - either from graphics processors with integrated DAC, or discrete DAC - to be driven with a current output. But how is that "faster"? In what sense?

What I also see in that linked Analog Devices datasheet is that they specify the peak video level as 0.714V, apparently according to RS/EIA-343A. Is the standard actually 0.714V rather than 0.700V as is commonly repeated everywhere? Seems like an odd value. Where does that come from?

[Benta]

EIA-343A has absolutely nothing to do with VGA. Google?

[vk6zgo]

Ah, I see. I did a bit more searching, and it seems it's common for VGA outputs - either from graphics processors with integrated DAC, or discrete DAC - to be driven with a current output. But how is that "faster"? In what sense?

What I also see in that linked Analog Devices datasheet is that they specify the peak video level as 0.714V, apparently according to RS/EIA-343A. Is the standard actually 0.714V rather than 0.700V as is commonly repeated everywhere? Seems like an odd value. Where does that come from?

0.714V is an artifact of the old NTSC system, & as far as I know, doesn't relate to VGA.
In any case, it pretty much counts as a "rounding error".

NTSC (& the old BW system in Australia) distinguished between "Black level" & "Blanking level" & had what was called "set up".

They both used "IRE" graticules. as the various video signal levels weren't nice, easy, fractions of 1.0V.

PAL, at least in the form it was introduced to Oz, eliminated "setup", Blanking to Peak White became 700mv, with Sync amplitude, 300mv.
This allowed the determination of video levels without the need for a special graticule.

[David Hess]

Ah, I see. I did a bit more searching, and it seems it's common for VGA outputs - either from graphics processors with integrated DAC, or discrete DAC - to be driven with a current output. But how is that "faster"? In what sense?

Current signalling is often faster than voltage signalling, especially if bipolar transistors can be used because they are faster than MOSFETs.  Current signalling is less effected by parasitic inductance which is a larger limitation than parasitic capacitance.

Back when VGA was designed, the fastest DACs were bipolar current output parts so fast graphics were based on them.

[Nominal Animal]

(TI THS7316 datasheet)

Your schematic is right.

I agree.  While the input voltage divider will work, it is not optimal, though; you should aim at 0.7V swing between zero and 100% color component (i.e. 0mV/233mV/467mV/700mV input voltage levels per color component), not 0.56V (0.7V-0.14V).   Consider using e.g. 680Ω, 3.7kΩ, 7.94kΩ.

I personally would replace U5 with a TI SN74LXC8T245, pull all eight signals through that, and power it and the THS7316 from a separate 3.3V regulator from the 5V source, to ensure nice, clean analog signal output.

[HwAoRrDk]

EIA-343A has absolutely nothing to do with VGA. Google?

I wasn't saying that EIA-343A was related to VGA, I was just wondering whether the signalling level was indirectly inherited from the older NTSC/monochrome/whatever standards, and whether everyone was using "0.7V" as rounded-down shorthand for 0.714V. That appears not to be the case. In fact, I found a copy of the VESA Video Signal Standard (VSIS) and it specifically states 0.7V as Max Luminance Voltage.

While the input voltage divider will work, it is not optimal, though; you should aim at 0.7V swing between zero and 100% color component (i.e. 0mV/233mV/467mV/700mV input voltage levels per color component), not 0.56V (0.7V-0.14V).   Consider using e.g. 680Ω, 3.7kΩ, 7.94kΩ.

Oh, I see what you mean. I'll be reducing the dynamic range between zero and maximum brightness levels.

But this is another thing I'm confused about. Is VGA signalling supposed to be between 0 and 700mV absolute, or have a voltage swing of 700mV peak-to-peak, where the minimum brightness level may not necessarily be 0V? Because the TH7316 has a minimum output of 280mV with 0V input, so it obviously can't do the former. But the VSIS specifications (see attached) seem to require the former.

I personally would replace U5 with a TI SN74LXC8T245, pull all eight signals through that, and power it and the THS7316 from a separate 3.3V regulator from the 5V source, to ensure nice, clean analog signal output.

So put the pre-DAC RGB signals through a buffer first, then DAC and THS7316? Why are we level-shifting from 3.3V to a separate 3.3V? I don't understand the reasoning for that. And powering the output side from a 3.3V source wouldn't give me 5V TTL sync signals.

[Benta]

VGA (and almost all other video signals) are AC coupled. DC restore is done on the receiving end using the syncs. The voltage levels are relative and thus specified as V_PP. If they are absolute, they'll be specified as 0...700 mV
.

[Nominal Animal]

But this is another thing I'm confused about. Is VGA signalling supposed to be between 0 and 700mV absolute, or have a voltage swing of 700mV peak-to-peak, where the minimum brightness level may not necessarily be 0V?

What Benta wrote above; 700mV peak-to-peak.

The TH7316 datasheet I linked to above even shows how you can AC-couple the outputs by adding capacitors between the outputs and the 75Ω resistors.

So put the pre-DAC RGB signals through a buffer first, then DAC and THS7316? Why are we level-shifting from 3.3V to a separate 3.3V? I don't understand the reasoning for that. And powering the output side from a 3.3V source wouldn't give me 5V TTL sync signals.

You are using a discrete two-bit voltage DAC per each color component.  This means that the exact voltage at the I/O pin output is critical.  A voltage level translator with dual supply and Schmitt trigger inputs yields very clean output voltages using the output side supply, even if the input side supply has some high-frequency switching noise (which you can expect when using a RP2040), for very little added cost.  The local 3.3V linear regulator thus ensures you have the cleanest analog output at and after the discrete DAC.  Using the same 3.3V source for the THS7316 means gives you the best chance of a clean output video and sync signals.

SN74LXC8T245 is a CMOS device, and when its outputs are driven from a 3.3V supply, the outputs are exactly compatible with (and have exactly the same threshold voltages as) 5V TTL.  Powering a CMOS output device at 3.3V definitely does give you 5V TTL output signals.

Sync signals are relatively low frequency — a few dozen Hz for Vsync, a few tens of kHz for Hsync — so you could use something like NXP 74HCT2G17 for the sync signals, powering it from 5V.  It would not change anything, though; you would just see slightly higher maximum voltages on the Hsync and Vsync lines, but the displays' input circuitry wouldn't care.  (Also, depending on how the display input circuitry works, having sync signals powered from a completely different rail than the analog video signals, might be problematic: for example in the case where the 5V varies but the 3.3V does not.)

NXP 74HCT2G17 is a CMOS device with TTL-compatible inputs and outputs, so it has almost as strong output drivers as normal CMOS devices do.
For SN74LXC8T245, see figure 6.1: when output is powered from 3.3V, the output high voltage drops linearly as a function of output current, so that 0mA the output is 3.3V and 3.0V at 25mA; similarly for output low voltage, so that 0mA the output is 0V and 0.2V at 25mA.  Remember that 5V TTL input high threshold is 2.0V, so even if you use SN74LXC8T245 at 3.3V, you'll still have at least 1V of headroom.

Actual TTL logic outputs are weaker.  For example, with TI SN74AHCT14, at 8mA output high drops by 0.7V, but it cannot source more than 20mA.  If we assume the high voltage drop is linear over output current, then at 20mA output, powered from 5V, the output voltage is approximately the same as SN74LXC8T245 powered from 3.3V!  Only if the output sources less current, is the actual TTL output voltage higher.