To be clear, since I put the voltage buffering emitter follower transistor after my signal source and before the caleading in to this amplifier I have REMOVED the cap which was parallel to the emitter resistor. The behaviour with the buffer and no emiter resistor bypass cap is what i was discussing in reply #32.
The output sine wave doesn't look distorted, certainly no huge distortions, perhaps a slight element of the rising/falling slopes being slightly more linear (hard to be sure but maybe slightly more constant-ish gradient when crossing the centre) than a perfect sine, but peaks still curve like a sine wave. No clipping, no huge distortion, no added spikes or ripples.
As far as gain goes, I'm ideally looking to gain this signal up as far as possible* without clipping from my 5V and ground rails, what I'm getting now is adequate, but more (up until the limitations of my voltage rails and any effects of the voltage drop in the transistor) would be desirable. I'd like to gain as much as I can, but only up to a point before I'd end up sacrificing accuracy to clipping or other phenomena. But it seems with the present situation I still can't seem to increase the gain above what it presently is by further adjusting resistors**, can anyone point me to a good webpage guide to not only calculating these but also to getting a proper feel for what is going on, my intuitions keep just considering transistors as digital switches despite all the other wonders I know they can accomplish. I have got Horowitz and Hill's book which has a BJT transistors chapter, but it perhaps discusses too many aspects of them at once.
*originally I had intended five fold because of what the input signal magnitude was originally, but as other sections of the circuit outside this thread's discussion have changed the signal input magnitude altered somewhat, it is now +300mV and -300mV about a centre and will stay such with any further changes to parts of circuits not discussed in this thread.
**might I have run in to limitations of the voltage drop already, if so I can tolerate it but if not I'd like to get more gain
What do you mean by "limitations of the voltage drop"?
Just to make sure I understand the complete circuit that for some reason you haven't shown us, you now have an emitter-follower feeding the common-emitter, and where they are connected you are measuring a 600 mV p-p signal going into the common-emitter. Is that correct?
I have attached three images from an LTSpice simulation of your circuit as I understand it. One is a frequency-response plot, one shows the input and output voltages, and one shows the voltages at the three legs of the BJT.
The maximum gain that will work depends on the input signal, so that knowing that really matters. Right now I calculate a mid-band gain of about 7.4, which agrees with the LTSpice frequency-response plot. But the plot shows that at 3 MHz your circuit response is already down -2 dB, and of course the Spice model will not be perfect for your particular bc337 so you may be down more (or less!). The fact that the input and output signals in the time-domain aren't exactly 180 degrees out of phase indicate the extra phase shift you expect to see in a low-pass filter when the response starts to fall.
What phase difference do you see between the input and output of the common-emitter? Could you post a screen shot?
By the way, a gain of 7.4 is unrealistic for a 5V rail and 300 mV input signal. You will need to reduce the nominal mid-band gain to optimize this circuit. I would think that a gain much more than about 6 or so would be tough.
One thing I would try immediately is to drop the collector and emitter resistors (by a factor of 10 perhaps) to increase the bias. This will increase the bandwidth of the common-emitter and also make probing easier and let you know if you have been trying to use your circuit above its operating band.
Another issue with the circuit is the bias point set by your voltage divider. The emitter bias point is at about 0.3 Volts, so if you input a 0.3 Volt sinusoid you may be driving the BJT into near cutoff when the input sine is at its most negative point. You may want to move the bias point to higher voltage. This will also make the circuit operation less dependent on the details of the particular transistor you pick. The plot I attached that shows the three signals at the BJT legs looks like it may be approaching cutoff, and at some point the base-collector junction is forward biased so it is entering saturation.
EDIT: In general I am unable to recommend web sites since that would require me to search for and read them to decide which ones were helpful. One video on the basics of the emitter-follower that shows AC and DC analysis of a BJT circuit is
There must be a good description of a common-emitter somewhere online... I learned this stuff from Microelectronics by Millman and Grabel, but the text by Sedra and Smith looks better. They do require that you already know basic circuit theory, though, and go through lots of math. If you want to maximize the gain from this circuit then, as pointed out by TimFox, you really need to learn and do the math or try trial and error with a simulation program. Note that this circuit will have limitations since you do not have a lot of control. I have attached a schematic that includes an extra bypassed resistor. The idea is that Rbp gives you control over the DC bias in a way that does not effect the gain. The design proces is similar to what TimFox indicated:
1. Fix the bias point - ideally would want the emitter to be 1.3 V or so (to make much less dependent on the transistor details) but to maximize voltage swing you might make the circuit less robust and lower it to 0.5V. You also need to pick a bias current (should probably be at least a few mA - so 10x what you have now) and a nominal gain.
2. Setup the voltage divider bias. Probably want the current through it to be at least 1/20 of the current through the transistor.
3. Do some algebra to determine the quiescent (DC) operating point with no signal input, leaving the resistor values as variables
4. Write a condition to avoid saturation. This is when Vcollector-Vemitter > Vsat where Vsat is the saturation voltage of the device (often 0.2V or so). This analysis will require an analysis of the AC circuit to add to the DC quiescent point. More algebra will yield a condition on the maximum allowed collector resistor, Rc.
5. Pick a collector resistor from a standard value that satisfies the condition from (4), then compute Re to get the gain you want. Once you know that you can then compute Rbp. Pick Cbp to be large enough so that at signal frequencies it is effectively a short.
If you don't have the time/inclination to learn the math, you can do this trial-and-error in a simulation program. In this case, though, you
1. setup the voltage divider to get something like 0.5V at the emitter (again, 1 V or more would make it less sensitive to devices). You need to pick a nominal bias current through the transistor in order to pick the sizes of the resistors for this voltage divider. Finally, you need to pick the gain.
2. pick Rc
3. pick Re to get the gain you want
4. pick Rbp to set the bias current.
5. run the simulation and see if you like the output. If you don't you can try a) reduce the gain and re-pick Re and Rbp. or b) return to 2 and pick a smaller Rc. Note that if you do b) then you need to keep the bias current and gain the same as you iterate. If you change them, then the maximum allowed value for Rc changes and you will do trial and error forever.
jason
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