Author Topic: SPI modes, which is correct?  (Read 631 times)

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Offline fabiodlTopic starter

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SPI modes, which is correct?
« on: July 11, 2023, 01:27:13 am »
In https://www.allaboutcircuits.com/technical-articles/spi-serial-peripheral-interface/

Mode 3: Clock phase is configured such that data is sampled on the rising edge of the clock pulse and shifted out on the falling edge of the clock pulse.

instead, in https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html
SPI Mode 3, CPOL = 1, CPHA = 1: CLK idle state = high, data sampled on the falling edge and shifted on the rising edge.

Which is correct?
 

Online ejeffrey

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Re: SPI modes, which is correct?
« Reply #1 on: July 11, 2023, 02:29:51 am »
The former is correct.

The CPHA definition  is in terms of "leading" and "trailing" edges where the meaning of leading and following depend on the "idle" state from CPOL.  It's a super confusing and annoying spec. 
 
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Offline ArdWar

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Re: SPI modes, which is correct?
« Reply #2 on: July 11, 2023, 02:52:15 am »
That AD article is incorrect. Their timing diagram, while technically correct and actually work, don't even help illustrating the difference.

For SPI CPHASE it's usually easier to remember the convention as leading/trailing edge instead of rising/falling edge
 
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Offline fabiodlTopic starter

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Re: SPI modes, which is correct?
« Reply #3 on: July 11, 2023, 11:29:33 pm »
Thank you. It was surprising that a page for beginners is correct and a silicon maker page is wrong.
« Last Edit: July 11, 2023, 11:32:09 pm by fabiodl »
 

Offline pdenisowski

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Re: SPI modes, which is correct?
« Reply #4 on: July 12, 2023, 09:55:57 am »
In https://www.allaboutcircuits.com/technical-articles/spi-serial-peripheral-interface/

Mode 3: Clock phase is configured such that data is sampled on the rising edge of the clock pulse and shifted out on the falling edge of the clock pulse.

instead, in https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html
SPI Mode 3, CPOL = 1, CPHA = 1: CLK idle state = high, data sampled on the falling edge and shifted on the rising edge.

Which is correct?

I actually used this exact same example in my video on SPI

https://youtu.be/0nVNwozXsIc?t=473

(Back up a minute or two for the explanation of CPOL and CPHA before the example)
 

Offline pdenisowski

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Re: SPI modes, which is correct?
« Reply #5 on: July 12, 2023, 10:00:58 am »
For SPI CPHASE it's usually easier to remember the convention as leading/trailing edge instead of rising/falling edge

Yes - I always refer to this as "leading / trailing" or even "first / second" edge to avoid confusion.
« Last Edit: July 12, 2023, 10:06:47 am by pdenisowski »
 


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