It would be better if the original poster stated what his end goal is with greater specificity so we can home in on what he needs. I suspect he is harboring the assumption that one form of jtag is universal and one dongle can be applied to all cases. This is only a partial truth. The lowest layer of jtag is pretty much the same but the internal state machines built on top of jtag vary from chip to chip. Which means you will want the adapter which has all the state machine kinks worked out by the manufacturer, and that is mostly software. SWD is a pincount/wire reduction of jtag that is specific to cortex arm processors but even here there are state machine specifics to each brand. For example I don't think a stlink-2 adapter can work on an lpc micro directly without fussing (could be wrong here). A close to universal solution would be a segger j-link or OCD with a ftdi2232h based adapter. These have the details worked out for many chips but I would still reach for the vendor specific adapter first. Ie, use an stlink2 for stm32 chips, pickit3 for pic32 ect.
Note the FTDI2232 is more capable than run of the mill usb2 to serial adapters, the general taxonomy:
for basic usb2 -> serial, ft232r ,cp2102 and others
for usb2 -> parallel fifo: ft245
the original altera bus byte blaster: usb2 -> ft245 + altera cpld then out to -> target fpga
some clone bus byte blasters: usb2 -> cypress usb express chip, or now a-days usb2-> stm32 chip!
The ft2232 has the equivalent of 2 FT245 fifo's + 2 spi/serial channels on board so it is all singing/all dancing
correction, I always conflate the names of altera's byte blaster with bus blaster designed by Ian Lesnet (dangerous prototypes).
The bus blaster is a FT2232 + xilinx CPLD jtag adapter if I recall correctly.
I wasn't suggesting you buy a jtagulator, it doesn't do what you want anyway. Or at least it didn't back when Joe made the video. You would still need a separate jtag adapter. Maybe current jtagulators have been upgraded. I just thought that the Joe Grand video was a fairly good intro into the steps required when reverse engineering.