5V TTL logic I/O translation

[Dead2]

I am working on a project that I hope I will be able to finalize and release as OSHW.

The project to design and build a simple 286 to 386SX adapter. (No FPU slot and no on-adapter caches like the commercial ones had.)
For the most part (after hours and hours of datasheet reading and comparison), this seems pretty straight forward, and I have created the relevant KiCad footprints and symbols, and have a partial schematic.

However, there is one remaining design issue remaining.

I have 3 input signals from the 386 cpu that need to be translated into 3 286 signals, and there is a total of 7 valid combinations.

I know the original commercial products that did this used GAL chips, and that looks like the most likely solution, but those are
impractical since they require a GAL-capable programmer, making it much more difficult for others to build a replica.
GAL chips have also not been produced for nearly 10 years, so they might not be the ideal choice.

Simpler solutions I have considered:
- I considered using EPROMs, but I expect that those will be too slow for this to actually work, since these are bus-control signals
  and should be able to work at up to ~16-20Mhz with unknown latency requirements.
- 74-series logic chips. This might work, but I have no idea how to build what I need.
- A bunch of discrete transistors. Should work, but I suspect I would need a lot of them, and probably easily gives design-errors.
  (A tool to generate this kind of translation using transistors or 74-series chips would have be cool)

So I thought I'd check with you guys whether you know of some great/simple solution to this.

The following are the relevant signals.

Code: [Select]

	286				Signal			386
M/IO	COD/INTA	S1	S2			M/IO	D/C	W/R
0	0		0	0	Interrupt ack	0	0	0
1	0		0	0	halt/shutdown	1	0	1
1	0		0	1	Mem data read	1	1	0
1	0		1	0	Mem data write	1	1	1
0	1		0	1	IO Read		0	1	0
0	1		1	0	IO Write	0	1	1
1	1		0	1	Mem code read	1	0	0

As you can see, the M/IO signal can be passed through as-is, but it is also needed as an input to distinguish between the other combinations.


Edit1: Fixed 386/286 typo, and changed TTL in subject to CMOS.
Edit2: Changed back to TTL in subject

[T3sl4co1l]

So uh, I'm not actually sure which ones are inputs and outputs.  Your typo leaves this ambiguous, and nowhere else seems to specify?

Are you trying to adapt a 80386SX CPU to a 286 motherboard/socket?  Or vice versa?

Also, anything about voltages?  "5V TTL" is specified in the title but most of these are CMOS... well, depending on version, I guess 286s were mostly HMOS (except for a few 3rd party sources that were CMOS?) while 386 is CMOS (or whatever exactly "CHMOS" was at the time)?  I guess that most versions of both are 5V so there's that, but TTL and CMOS aren't quite compatible.  (LVCMOS at 3.3V is pretty close to 5V TTL,

Yes, 74 logic would seem desirable, perhaps 74F or ABT for TTL levels, or 74AC or LVC for CMOS levels (with ACT as an option for TTL input compatibility).  Three or four signals are easy enough to solve on a 2D grid (Karnaugh map), probably worse case two or three chips can do it.  Which takes up about as much space as the CPU itself, which, well, you can see why PAL/GALs were so popular back then.

Tim

[rstofer]

It looks like you have 4 inputs and 3 outputs (just guessing).  Create a 4x4 Karnaugh Map and minimize the logic.  It looks like the map will be pretty sparse (half of the input combinations don't have an output specification) and this allows for a lot of minimization.

OTOH, the map may not be sparse, the data given may just be wrong.  What is supposed to happen for unspecified input combinations?  The thing about using Karnaugh Maps is that you can assign unspecified boxes to have whatever value results in the most minimization.  That's great as long as the unspecified conditions don't result in an output that is invalid.

My guess is that you will have to define the outputs for all 16 input combinations and then try to minimize it with mapping.  Or, some maybe input combinations just can't exist so we don't care what the output would be.  This allows for an 'x' in the box and more minimization.

Make sure you know what the output should be for every possible input combination and which input combinations can't exist.

[T3sl4co1l]

Also, you can chain some min/max terms to get better optimization at the cost of propagation delay.  You'll also often generate transient states (runt pulses, glitches) from such logic, as the signals propagate through different depths of gates on their way through.  So be careful.  It doesn't look like these signals are edge-triggered?  So that's probably not an issue, just something to keep in mind.

The least possible gate delay, with the most general approach, is to form all min-terms, then all max-terms (or vice-versa).  Which is what the PAL does: it's an array of inverters (so each input and its complement is available), crosslinks (to wire some combination of inputs and min/max gates), AND or OR gates, then OR or AND gates.  Exactly which combination is used, depends on the technology, some use minterms (AND then OR), some the other way.  I forget if one or the other is more common?  Also there's a certain fanout, a certain supply of each, so if you need like 20-goddamn minterms and the PAL only has 12 inside, you'll have to invert it (use maxterms, which probably won't need as many), or whatever.

Put another way: for every combination of inputs that should yield an active (or inactive) output, collect that combination of normal/complemented inputs together.  For inputs A, B, C, etc., form the product A * /B * C * ..., inputs complemented as needed.  Then add together all these terms, A*/B*C + /A*B*C + ..., whatever it is.  Clearly the gate delay is at most one inverter, one AND and one OR, which if they're equal is a total of three gate delays, simple.

But with such a small space, this is easy to solve.

Specifically, let's see, with as many as 16 possible input states, up to half as many min/max terms might have to be formed and collected -- that would require four inverters (one for each input), and for each output, eight 4-input ANDs and one 8-input OR).  I suppose about 9 chips absolute worst case.

It looks like it's going to be much simpler than that, and plus you can use standard functions to optimize certain convenient (or pathological) patterns.  Namely, AND-OR-INVERT gates are a thing; muxes are wonderful; and, XOR implements the checkerboard pattern that otherwise requires worst-case min and max terms.  Probably, using standard logic, the worst-case is closer to 1/4th the total number of states, or 4 terms?  Worst case gate delay might be a few more than canonical minimum, not sure.

Tim

[jmelson]

This looks like it might be doable with a Xilinx XC9500XL family part, which runs off 3.3 V but is 5V tolerant, and would be TTL compatible.
You can download Xilinx's tools for free (web pack) and simulate the inputs with a VHDL test bench to verify it covers all the valid logic states.
Since you will have pins left over, you could likely handle any other logic required in the same part.

Jon

[oPossum]

I know the original commercial products that did this used GAL chips, and that looks like the most likely solution, but those are
impractical since they require a GAL-capable programmer, making it much more difficult for others to build a replica.
GAL chips have also not been produced for nearly 10 years, so they might not be the ideal choice.

Microchip still makes GALs.

https://www.microchip.com/ParamChartSearch/chart.aspx?branchID=30024

The ATF16V8, ATF20V8 and ATF22V10 can be programmed with a $50 TL866 programmer.

[Dead2]

Sorry for being unclear.

I want to put a 386SX cpu into a 286 motherboard.
The 386 outputs bus control signals on 3 pins, but the 286 motherboard will expect bus control signals on 4 pins.
One of the four pins is a direct copy from the 386, but the rest need to be translated. So a 3-to-3 pin translation.

The invalid combinations are just that, invalid and as far as I can tell those should never happen. Of course they need to be mapped to something,
but it seems like any combination is ok for that. These signals are pretty much selectors that tell the bus what you want to communicate with,
and whether it is for read or write, then the chipset handles the switching according to that and raises the bus_ready signal (no conversion needed).
What actually triggers the bus switching operation is something I need to do another more thorough read of the documentation to find.
It is not edge triggered as far as I can tell, but getting too much latency compared to what triggers the read would obviously be bad.

Both cpus use a 5V power supply and signals. (3.3V versions exist, but that would just complicate things a lot more).

The "Karnaugh map" thing looks very interesting, I am not quite sure how I would implement that using 74-logic chips though.


As far as FPGAs go, I consider them to be even worse than GALs for this project, since they are AFAICT more expensive and harder to program for the end-user.
The goal is to have something that only requires some decent soldering skills.

I found the ATF CPLD in my research before posting here, those are Atmel chips, and are according to what I found on the internet, horrible when it comes to actual software or documentation support.
The ATF22V10 is apparently one of the worst, and you can read about that here: https://www.ecstaticlyrics.com/electronics/ATF22V10C/

[Dead2]

Oh, both the original 286 and the 386 are 5V CMOS. (286 states "Static CMOS", and the 386 says "High Speed CHMOS IV Technology" or just "0.8micron CMOS technology" depending on variant).

If that means they are not actually using TTL signaling, then that is something I was unaware of, so please inform me.

[T3sl4co1l]

The important parameters are V_IH and V_IL for inputs, and V_OH and V_OL for outputs: typically CMOS has a 30-70% VDD threshold range, and outputs near the rails.

NMOS and HMOS (or most HMOS anyway, as I understand it) behave very much like TTL, with both ranges biased downward -- in other words, TTL-compatible (V_IL < 0.8V, V_IH > 2V).

Tim

[T3sl4co1l]

So, writing out the truth tables individually, we can see by inspection:

Code: [Select]

		386				286
M/IO		D/C		W/R		COD
0		0		0		0
0		0		1		X
0		1		0		1
0		1		1		1
1		0		0		1
1		0		1		0
1		1		0		0
1		1		1		0

		386				286
M/IO		D/C		W/R		S1
0		0		0		0
0		0		1		X
0		1		0		0
0		1		1		1
1		0		0		0
1		0		1		0
1		1		0		0
1		1		1		1

		386				286
M/IO		D/C		W/R		S2
0		0		0		0
0		0		1		X
0		1		0		1
0		1		1		0
1		0		0		1
1		0		1		0
1		1		0		1
1		1		1		0

COD = /MIO*DC*/WR + /MIO*DC*WR + MIO*/DC*/WR [+ /MIO*/DC*WR]
S1 = [/MIO*/DC*WR +] /MIO*DC*WR + MIO*DC*WR
S2 = [/MIO*/DC*WR +] /MIO*DC*/WR + MIO*/DC*/WR + MIO*DC*/WR
('/' = negation of following signal or parentheses, '*' = AND, '+' = OR; brackets: optional term)

So, these can be synthesized with at most: three NOT gates, eight 3-in AND gates and three 3-in OR gates, writing out the minterms explicitly.  Apply boolean algebra steps to simplify: collect common factors, apply identities, and if you like, share minterms (or maxterms, or XOR terms if they look useful?) between outputs.  For example, there are only five unique minterms, so we can already save on ANDs.  (3-input gates come in triples, so you'd still need four chips.  That's not bad.  Maybe with some NAND/NOR/XOR and clever spotting, one chip can be saved, maybe two?)

Tim

[exmadscientist]

Logic Friday did a pretty good job on this one! (For once.)

Starting from Tim's eqations above, reformatted into Logic Friday syntax (actually ancient-Berkeley-scary-tools syntax, since LF is just a wrapper for 30-year-old tools) and minimizing:

Entered:
COD = MIO'*DC*WR' + MIO'*DC*WR + MIO*DC'*WR' + MIO'*DC'*WR;
S1 =  MIO'*DC'*WR + MIO'*DC*WR + MIO*DC*WR;
S2 =  MIO'*DC'*WR + MIO'*DC*WR' + MIO*DC'*WR' + MIO*DC*WR';

Minimized:
COD = MIO' DC' WR + MIO DC' WR' + MIO' DC ;
S1 = MIO' DC' WR + DC WR;
S2 = MIO' DC' WR + MIO DC' WR' + DC WR';

Then if we tell it to implement in gates and twiddle its allowed devices a bit, we get the attached implementation, which it claims is just 3 ICs. Two of those are obvious enough, a 74'00 quad 2-NAND and an '04 hex inverter. The muxes are a little trickier. There is a 2G97 that will do it, but it's not very available and isn't getting better. A pair of '1G97s would do it, but that's 4 ICs, even if two are small. To actually get the claimed 3 IC implementation, we can note that the S selection inputs are the same, so a '157 will do the job. I'd probably usually rather have the smaller one, but the program wasn't lying, you really can do it in 3 chips.

I'm sure that's not the best conceivable implementation, but not bad for something that took longer to write up than to find. The old magic is still good for something!

[T3sl4co1l]

Interesting, [5] could be an XOR, but as the inverter is free* and the mux can be dual (or more), it's not really an optimization.  (I'd rather go for smaller BOM -- why bother getting a '1G86 at all, when the '1G97 is needed regardless, and two will do?)

*Hmm, well, then only three inverters are needed which could be a '3G04, but a TSSOP '04 isn't much larger, and the NAND (and MUX if '157 is chosen) can be TSSOP too.

I might actually be concerned about the 7-gate maximum delay path through this, though -- it's probably worth spending a few more gates to keep that low.

Tim

[amyk]

cod = !m/io & d/c | m/io & d/c nor w/r
s1 = d/c or w/r
s2 = not w/r

[jmelson]

As far as FPGAs go, I consider them to be even worse than GALs for this project, since they are AFAICT more expensive and harder to program for the end-user.

The XC9500XL line are not FPGAs, but essentially super-GALs.  The XC9536XL is a little over $1 in single quantity in the 44-pin flat pack.  Yes, you do need a JTAG pod, but the Chinese are cloning the Xilinx Platform Cable USB pretty cheaply.  The design and sim software are downloadable for free to most countries.  They do take a little while to learn the ins and outs, but are not too bad.  I haven't built anything up with TTL chips in about 20 years now.  Instead of a bunch of DIP sockets and wire-wrap wire, I pick the appropriate-sized device and write some VHDL code, try it in simulation and then try in the real world.  Instead of having to rip out wires and add a few more chips, you just change the VHDL and test again.  MUCH easier!

Jon

[Dead2]

The XC9500XL line does look very interesting indeed, I will have to get some of those and have a go at using them.
But not in this project, as I'd still like to avoid any need for programming. Also, although those chips have 5V tolerant IO pins, the docs say they still need 3.3V power supply, meaning I would need to add voltage regulators etc.

[Dead2]

cod = !m/io & d/c | m/io & d/c nor w/r
s1 = d/c or w/r
s2 = not w/r

Your S2 definition is wrong. In the all-zero instance, it needs to stay zero when input is zero. (I had already looked into that simplification myself)

Edit:
Your COD definition seems good.
But I cannot get the s1 definition to make any sense at all, is that 'or' something other than a 'logical or' returning 1 if either is 1?

Edit2:
Or perhaps I just don't understand the language/formulas used here..

[Dead2]

I must say I love Logic Friday, I had not heard of that but I knew something like that must exist somewhere, so thank you for that tip.

I have done a little experimentation with it myself, and I found a solution that is simpler than the one posted above. It looks correct to me,
but it would be great if someone more experienced could have a look to see whether I did something wrong.

Entered by truthtable:

Code: [Select]

COD/INTA = M/IO' D/C W/R' + M/IO' D/C W/R + M/IO D/C' W/R';
S1 = M/IO' D/C W/R + M/IO D/C W/R;
S2 = M/IO' D/C W/R' + M/IO D/C' W/R' + M/IO D/C W/R';

Minimized joint:

Code: [Select]

COD/INTA = M/IO D/C' W/R' + M/IO' D/C ;
S1 = D/C W/R;
S2 = M/IO D/C' W/R' + D/C W/R';

Minimized independent:

Code: [Select]

COD/INTA = M/IO' D/C  + M/IO D/C' W/R';
S1 = D/C W/R;
S2 = M/IO W/R' + D/C W/R';

This produced the shortest/simplest gate diagram.

Code: [Select]

IC	Qty
Quad 2-Input NAND	1
Quad 2-Input NOR	1
Quad 2-Input AND	1
TOTAL PACKAGES	3

I have used the 'Trace Gate Logic' function, and it all seems to be correct.

[T3sl4co1l]

Not bad, four gate delays seems reasonable.

The AND can be changed to a NAND, with the last NOR inverting its output; but that still needs another chip.  Or changed to a NOR with two inverters in front of it, which still needs another chip but it's only a 2G04, which might be more agreeable than plunking down another '00 or '02.

Tim

[Dead2]

So, signal voltages..

AMD 80C286:

Code: [Select]

		Min		Max
VIL		-0.5		0.8
VIH		2.0		Vcc+0.5
VOL				0.4
VOH IOH=-2mA	3.0
VOH IOH=-100mA	Vcc-0.4

Intel 386SX:

Code: [Select]

		Min		Max
VIL		-0.3		0.8
VIH		2.0		Vcc+0.3
VOL				0.45
VOH IOH=-0.9mA	2.4V
VOH IOH=-0.18mA	Vcc-0.5

Cyrix Cx486SLC:

Code: [Select]

		Min		Max
VIL		-0.3		0.8
VIH		2.0		Vcc+0.3
VOL				0.45
VOH IOH=-1mA 	2.4
VOH IOH=-0.2mA 	Vcc-0.5

This looks pretty similar to me. Only the first VOH is lower with the 386 cpus, but still above 2V, so if I understand correctly it should still register correctly.
Might have to look up some chipset specs to make sure.

From what I understand, these are TTL voltages, am I correct?

(Note that the Cx486SLC is in fact more of a 386SX than a 486, but it has a small cache and it understands 486 instructions.
 Unclear on whether it supports all 486 instructions or only the ones used by applications and not OS-level ones).

[T3sl4co1l]

Yeah, that looks TTL compatible.

Tim

[amyk]

cod = !m/io & d/c | m/io & d/c nor w/r
s1 = d/c or w/r
s2 = not w/r

Your S2 definition is wrong. In the all-zero instance, it needs to stay zero when input is zero. (I had already looked into that simplification myself)

Edit:
Your COD definition seems good.
But I cannot get the s1 definition to make any sense at all, is that 'or' something other than a 'logical or' returning 1 if either is 1?

Edit2:
Or perhaps I just don't understand the language/formulas used here..

Sorry, I was just going by T3sl4co1l's tables above: https://www.eevblog.com/forum/beginners/5v-ttl-logic-io-translation/msg3362428/#msg3362428 and yes, s1 should've been d/c and w/r.

[jmelson]

The XC9500XL line does look very interesting indeed, I will have to get some of those and have a go at using them.
But not in this project, as I'd still like to avoid any need for programming. Also, although those chips have 5V tolerant IO pins, the docs say they still need 3.3V power supply, meaning I would need to add voltage regulators etc.

YUP, I sure wish they just kept the older 5V XC9500 series alive for us luddites that are still in the 5V world.  But, throwing in a tiny regulator is really not that big a deal.  Panasonic used to make a TINY regulator in an SOT23-size package that was ideal, but of course they discontinued that part.  ARRGH!  I now use LM1117-type regulators.

Jon