Right, the solution is actually easier.
Your premise I think assumes a single switch turning on and off, the output being implicitly pulled to GND by load resistance. That is, the source impedance alternates between nearly zero (Rds(on) plus DC supply impedance) and nearly infinity (leakage). This is how you most often drive a relay coil for example, or LEDs (when not driving them from logic pins, that is).
The fact that the impedance is changing, makes analysis very difficult. It is not a linear, time-invariant (LTI) system. If you put any arbitrary load on there (some RLC network, or even just some complex impedance at the driven frequency and harmonics), it's difficult to predict what will happen. Further nonlinearities are likely to get involved. For example if the load is inductive, probably when the switch turns off, the voltage flies back and is clamped either by the switch's own avalanche breakdown (a hazardous operating mode) or an opposing switch's parasitic diode. (Or if neither, it probably just blows up after that one cycle.)
If we instead provide means to pull the load back down to zero, or to -V, alternating with the switch to +V, now the output is enabled at all times, and its output impedance is well defined, or much better anyway. (There is the brief period when both switches are off, where voltage can be allowed to freewheel a bit; the impedance for such short periods is determined by switch capacitances and the stray inductance between them, and so the average impedance at the driven frequency is an average between these; it's not nearly an undefined impedance, like it would be in the on-off case.)
And with a constant low inverter impedance, we can use a PWM filter of the one-port-shorted type, providing termination at the output port with a shunt R+C (and perhaps a series L or R||L as well, so that low impedance loads don't screw it up by shorting out the R+C). This will be a L-input lowpass filter, and that first inductor takes the brunt of the PWM ripple as the main filter inductor so must be sized accordingly.
Put another way: in the one case, we really don't have any analytical tool to bring to bear; the best we can do is shove a representative model into SPICE and simulate it from timestep to timestep. In the other case, our LTI assumptions are satisfied (or more nearly so), and we can use traditional AC steady-state analysis, and network theory and etc., to design an efficient filter for it.
There are other situations in drives and controls, where it pays to keep the system linear, or only permit certain exceptions. Like, you might have a power supply that should be linear so its loop can be compensated (and that compensation is adequate for all V/I output settings), but make an exception that, under startup or fault conditions say, the compensation is bypassed to allow quick startup/shutdown. Or for a bench supply (CV/CC output mode), the compensation for each respective error amp (voltage and current) might be disabled or clamped, such that the other is able to catch the output quickly after its variable crosses the threshold, thus reducing integrator windup (which causes a big excursion in voltage and/or current when crossing between CC/CV).
Tim